STE36N50A Datasheet, PDF (3/8 Pages) STMicroelectronics – N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR IN ISOTOP PACKAGE

STE36N50A
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symb ol
t_d(on)
t_r
(di/ d t) o n
Q_g
Q_gs
Qgd
Parameter
Turn-on Time
Rise Time
Turn-on Current Slope
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Test Conditions
V_DD = 250 V I_D = 18 A
R_G = 4.7 Ω
V_GS = 10 V
(see test circuit, figure 1)
VDD = 400 V ID = 36 A
RG = 4.7 Ω
VGS = 10 V
(see test circuit, figure 3)
V_DD = 400 V I_D = 36 A V_{G S} = 10 V
Min.
Typ.
45
85
700
295
35
145
Max.
65
120
Unit
ns
ns
A/µs
nC
nC
nC
SWITCHING OFF
Symb ol
tr(Vof f)
tf
t_c
Parameter
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Conditions
VDD = 400 V ID = 36 A
RG = 4.7 Ω VGS = 10 V
(see test circuit, figure 3)
Min.
Typ.
100
45
160
Max.
140
65
225
Unit
ns
ns
ns
SOURCE DRAIN DIODE
Symb ol
Parameter
Test Conditions
I_{S D}
I _SDM(•)
Source-drain Current
Source-drain Current
(pulsed)
VSD (∗) Forward On Voltage
ISD = 36 A VGS = 0
t_rr
Reverse Recovery
Time
Qrr Reverse Recovery
Charge
I_SD = 36 A di/dt = 100 A/µs
V_DD = 100 V T_j = 150 ^oC
(see test circuit, figure 3)
IRRM Reverse Recovery
Current
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Min.
Typ.
Max.
36
144
Unit
A
A
1.4
V
1
µs
29
µC
58
A
Safe Operating Areas
Thermal Impedance
3/8