M25P10 Datasheet, PDF (3/21 Pages) STMicroelectronics – 1 Mbit Low Voltage Paged Flash Memory With 20 MHz Serial SPI Bus Interface

Figure 3. Microcontroller and Memory Devices on the SPI Bus
SPI Interface with ^SDO
(CPOL, CPHA) = SDI
('0', '0') or ('1', '1') _SCK
Master
(ST6, ST7, ST9,
ST10, Others)
CS3 CS2 CS1
CQD
M25P10
S
CQD
M25P10
S
M25P10
CQD
M25P10
S
AI03746
Once bit 7 (SRWD) of the status register has been
set to 1, the possibility to rewrite the SR depends
on the logical level present at pin W:
– If W pin is high, it will be possible to rewrite the
status register after having set the WEL (Write
Enable Latch).
– If W pin is low, any attempt to modify the status
register will be ignored by the device even if the
WEL was set. As a consequence: all the data
bytes in the memory area software protected
(SPM) by the BPi bits of the status register are
also hardware protected against data
modification and can be seen as a Read Only
memory area. This mode is called the Hardware
Protected Mode (HPM).
It is possible to enter the Hardware Protected
Mode (HPM) by setting SRWD bit after pulling
down the W pin or by pulling down the W pin after
setting SRWD bit.
The only way to abort the Hardware Protected
Mode once entered is to pull high the W pin.
If W pin is permanently tied to high level, the
Hardware Protected Mode will never be activated
and the memory will only allow the user to
software protect a part of the memory with the BPi
bits of the status register.
All protection features of the device are
summarized in Table 3.
Figure 4. Hold Condition Activation
CLOCK
HOLD PIN
MEMORY
STATUS
ACTIVE
HOLD
ACTIVE
HOLD
ACTIVE
AI02029B
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