HCC4724B Datasheet, PDF (3/14 Pages) STMicroelectronics – 8 BIT ADDRESSABLE LATCH

LOGIC DIAGRAM
HCC/HCF4724B
Definition of WRITE DISABLE ON Time
MODE SELECTION
TYPE WD
R
Addressed Unaddressed
Latch
Latch
A
0
0 Follows Data Hold Previous
State
B
0
1 Follows Data Reset to ”0”
(Active High
8-Channel
Demultiplexer)
C
1
0
Hold Previous State
D
1
1 Reset to ”0” Reset to ”0”
WD = WRITE DISABLE R= RESET
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