HCC4724B Datasheet, PDF (1/14 Pages) STMicroelectronics – 8 BIT ADDRESSABLE LATCH

HCC4724B
HCF4724B
. SERIAL DATA INPUT - ACTIVE PARALLEL
OUTPUT
. STORAGE REGISTER CAPABILITY - MASTER
CLEAR
. CAN FUNCTION AS DEMULTIPLEXER
. STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTER
. 100% TESTED FOR QUIESCENT CURRENT
AT 20V
. MAXIMUM INPUT CURRENT OF 1µA AT 18V
. ^{(full package-temperature range), 100nA AT 18V}
AND 25^oC
NOISE MARGIN (full package-temperature
.. range) = 1V AT VDD = 5V, 2V AT VDD = 10V, 2.5V
AT V_DD = 15V
5V, 10V, AND 15V PARAMETRIC RATINGS
MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD N. 13A, ” STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ’ B
’ SERIES CMOS DEVICES ”
..APPLICATION
MULTI-LINE DECODERS
A/D CONVERTERS
DESCRIPTION
The HCC/HCF4724B 8-bit addressable latch is a
serial-input, parallel-output storage register that can
perform a variety of functions.
Data are inputted to a particular bit in the latch when
that bit is addressed (by means of inputs A0, A1, A2)
and when WRITE DISABLE is at low level. When
WRITE DISABLE is high, data entry is inhibited
however, all 8 outputs can be continuously read in-
dependent of WRITE DISABLE and address inputs.
A master RESET input is available, which resets all
bits to a logic ” 0 ” level when RESET and WRITE
DISABLE are at a high level. When RESET is at a
high level, and WRITE DISABLE is at a low level, the
latch acts as a 1-of-8 demultiplexer ; the bit that is
addressed has an active output which follows the
data input, while all unaddressed bits are held to a
logic ” 0 ” level.
8 BIT ADDRESSABLE LATCH
EY
(Plastic Package)
F
(Ceramic Package)
M1
(Micro Package)
C1
(Chip Carrier)
ORDER CODES :
HCC4724BF
H CF 4724 BM 1
HCF4724BEY
H CF 4724 BC 1
PIN CONNECTIONS
September 1988
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