ESDAXXSCX Datasheet, PDF (3/10 Pages) STMicroelectronics – QUAD TRANSIL™ ARRAY FOR ESD PROTECTION

ESDAxxSCx
1. CALCULATION OF THE CLAMPING VOLTAGE USE OF THE DYNAMIC RESISTANCE
The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB designers need to
calculate easily the clamping voltage V_CL. This is why we give the dynamic resistance in addition to the
classical parameters. The voltage across the protection cell can be calculated with the following formula:
V_CL = V_BR + R_d I_PP
Where I_PP is the peak current through the ESDA cell.
As the value of the dynamic resistance remains stable for a surge duration lower than 20ms, the 2.5ms
rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic
phenomenon during the measurement of R_d.
2. DYNAMIC RESISTANCE MEASUREMENT
The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the
classical 8/20µs and 10/1000µs surges.
Figure 3: 2.5µs duration measurement wave
I
Ipp
2µs
t
tp = 2.5µs
Figure 4: Peak power dissipation versus initial
junction temperature
Figure 5: Peak pulse power versus exponential
pulse duration (T_j initial = 25 °C)
PPP[Tj initial] / PPP[Tj initial=25°C]
1.1
PPP(W)
5000
1.0
0.9
0.8
ESDA5V3SC5/SC6
&
0.7
ESDA6V1SC5/SC6
1000
0.6
0.5
ESDA14V2SC5/SC6
0.4
ESDA17SC6
ESDA19SC6
0.3
ESDA25SC6
0.2
0.1
Tj initial (°C)
0.0
0
25
50
75
100
125
150
100
1
tp(µs)
10
100
3/10
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