AN970 Datasheet, PDF (3/10 Pages) STMicroelectronics – SPI COMMUNICATION BETWEEN ST7 AND EEPROM

SPI COMMUNICATION BETWEEN ST7 AND EEPROM
2 ST72264 CONFIGURATION
2.1 I/O CONTROL
Four pins of the ST72264 are used:
- The 3 data and clock SPI pins (SCK, MOSI, MISO).
- An output pin to select and deselect the M95xxx.
- SS pin to select master or slave mode.
In our application, the output for selecting the M95xxx is pin 3 of Port B. It is configured as
output push-pull (refer to the datasheet for details).
2.2 SPI PERIPHERAL
2.2.1 General
This peripheral is configured with the SPI Control Register.
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SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
The output must be enabled (SPE = 1).
If the SS pin is high (see SPICSR), the ST72264 can be declared as master by setting the
MSTR bit.
The transmission speed, in master mode, is selected using the SPR0, SPR1 and SPR2 bits.
The CPOL and CPHA bits define the timing characteristics.
When the SPIE bit is set, SPI interrupts are enabled (not used in our case).
2.2.2 SS software configuration
The SS pin can be fixed by hardware, either connected to Vss (for a slave configuration) or to
Vdd (for a master configuration). But it can also be software driven through the SPICSR reg-
ister (SSM and SSI bits) :
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SPIF WCOL OVR MODF - SOD SSM SSI
To set the master configuration (as in our case) : SSM=1 and SSI=1
To set the slave configuration: SSM=1 and SSI=0
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