TDA7513T Datasheet, PDF (27/59 Pages) STMicroelectronics – SINGLE-CHIP FM/AM TUNER WITH STEREO DECODER AND AUDIO PROCESSOR

TDA7513T
using the Quality detector output. During this time the multipath detector is automatically switched to a
small time constant.
One dedicated pin (#RDSMUTE) is provided in order to separate the audioprocessor-mute and stereode-
coder AF-functions.
5.10 I²C-Bus Interface
I²C bus protocol is supported. This protocol defines any device that sends data onto the bus as a trans-
mitter, and the receiving device as the receiver.
The device that controls the transfer is a master and device being controlled is the slave. The master will
always initiate data transfer and provide the clock to transmit or receive operations. The present device
always acts as slave, both in transmission and in reception mode.
5.10.1Data Transition
Data transition on the SDA line must only occur when the clock SCL is LOW. SDA transitions while SCL
is HIGH will be interpreted as START or STOP condition.
5.10.2Start Condition
A start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a stable HIGH
level. This "START" condition must precede any command and initiate a data transfer onto the bus. The
device continuously monitors the SDA and SCL lines for a valid START and will not response to any com-
mand if this condition has not been met.
5.10.3Stop Condition
A STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at a stable
HIGH level. This condition terminates the communication between the devices and forces the bus inter-
face of the device into the initial condition.
5.10.4Acknowledge
Indicates a successful data transfer. The transmitter will release the bus after sending 8 bits of data. Dur-
ing the 9th clock cycle the receiver will pull the SDA line to LOW level to indicate it received the eight bits
of data.
5.10.5Data Transfer
During data transfer the device samples the SDA line on the leading edge of the SCL clock. Therefore, for
proper device operation the SDA line must be stable during the SCL LOW to HIGH transition.
5.10.6Device Addressing
To start the communication between two devices, the bus master must initiate a start instruction se-
quence, followed by an eight bit word corresponding to the address of the device.
The device recognizes the following two addresses:
1100010d
tuner part address
1000110d
stereo decoder / audio processor address (APSD)
The last bit of the start instruction defines the type of operation to be performed:
– when set to "1", a read operation is selected (data are transferred from the device to the master)
– when set to "0", a write operation is selected (data are transferred from the master to the device)
The device connected to the bus will compare its own hardwired addresses with the slave address being
transmitted after detecting a START condition.
After this comparison, the device will generate an "acknowledge" on the SDA line and will perform either
a read or a write operation according to the state of the R/W bit.
27/59