M58WR064T Datasheet, PDF (26/81 Pages) STMicroelectronics – 64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory

M58WR064T, M58WR064B
CONFIGURATION REGISTER
The Configuration Register is used to configure
the type of bus access that the memory will per-
form. Refer to Read Modes section for details on
read operations.
The Configuration Register is set through the
Command Interface. After a Reset or Power-Up
the device is configured for asynchronous page
read (CR15 = 1). The Configuration Register bits
are described in Table 9. They specify the selec-
tion of the burst length, burst type, burst X latency
and the Read operation. Refer to Figures 6 and 7
for examples of synchronous burst configurations.
Read Select Bit (CR15)
The Read Select bit, CR15, is used to switch be-
tween asynchronous and synchronous Bus Read
operations. When the Read Select bit is set to ’1’,
read operations are asynchronous; when the
Read Select bit is set to ’0’, read operations are
synchronous. Synchronous Burst Read is support-
ed in both parameter and main blocks and can be
performed across banks.
On reset or power-up the Read Select bit is set
to’1’ for asynchronous access.
X-Latency Bits (CR13-CR11)
The X-Latency bits are used during Synchronous
Read operations to set the number of clock cycles
between the address being latched and the first
data becoming available. For correct operation the
X-Latency bits can only assume the values in Ta-
ble 9, Configuration Register.
The correspondence between X-Latency settings
and the maximum sustainable frequency must be
calculated taking into account some system pa-
rameters. Two conditions must be satisfied:
1. Depending on whether t_{AVK_CPU} or t_DELAY is
supplied either one of the following two
equations must be satisfied:
(n + 1) t_K ≥ t_ACC - t_{AVK_CPU} + t_{QVK_CPU}
(n + 2) t_K ≥ t_ACC + t_DELAY + t_{QVK_CPU}
2. and also
t_K > t_KQV + t_{QVK_CPU}
where
n is the chosen X-Latency configuration code
t_K is the clock period
t_{AVK_CPU} is clock to address valid, L Low, or E
Low, whichever occurs last
t_DELAY is address valid, L Low, or E Low to clock,
whichever occurs last
t_{QVK_CPU} is the data setup time required by the
system CPU,
t_KQV is the clock to data valid time
t_ACC is the random access time of the device.
Refer to Figure 6, X-Latency and Data Output
Configuration Example.
Wait Polarity Bit (CR10)
In synchronous burst mode the Wait signal indi-
cates whether the output data are valid or a WAIT
state must be inserted. The Wait Polarity bit is
used to set the polarity of the Wait signal. When
the Wait Polarity bit is set to ‘0’ the Wait signal is
active Low. When the Wait Polarity bit is set to ‘1’
the Wait signal is active High (default).
Data Output Configuration Bit (CR9)
The Data Output Configuration bit determines
whether the output remains valid for one or two
clock cycles. When the Data Output Configuration
Bit is ’0’ the output data is valid for one clock cycle,
when the Data Output Configuration Bit is ’1’ the
output data is valid for two clock cycles.
The Data Output Configuration depends on the
condition:
s t_K > t_KQV + t_{QVK_CPU}
where t_K is the clock period, t_{QVK_CPU} is the data
setup time required by the system CPU and t_KQV
is the clock to data valid time. If this condition is not
satisfied, the Data Output Configuration bit should
be set to ‘1’ (two clock cycles). Refer to Figure 6,
X-Latency and Data Output Configuration Exam-
ple.
Wait Configuration Bit (CR8)
In burst mode the Wait bit controls the timing of the
Wait output pin, WAIT. When the Wait bit is ’0’ the
Wait output pin is asserted during the wait state.
When the Wait bit is ’1’ (default) the Wait output
pin is asserted one clock cycle before the wait
state.
WAIT is asserted during a continuous burst and
also during a 4 or 8 burst length if no-wrap config-
uration is selected. WAIT is not asserted during
asynchronous reads, single synchronous reads or
during latency in synchronous reads.
Burst Type Bit (CR7)
The Burst Type bit is used to configure the se-
quence of addresses read as sequential or inter-
leaved. When the Burst Type bit is ’0’ the memory
outputs from interleaved addresses; when the
Burst Type bit is ’1’ (default) the memory outputs
from sequential addresses. See Tables 10, Burst
Type Definition, for the sequence of addresses
output from a given starting address in each mode.
Valid Clock Edge Bit (CR6)
The Valid Clock Edge bit, CR6, is used to config-
ure the active edge of the Clock, K, during Syn-
chronous Burst Read operations. When the Valid
Clock Edge bit is ’0’ the falling edge of the Clock is
26/81