TDA7513T_07 Datasheet, PDF(25/84 Page) STMicroelectronics – Single chip FM/AM tuner with stereo decoder and audio processor

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TDA7513T_07 Datasheet, PDF (25/84 Pages) STMicroelectronics – Single chip FM/AM tuner with stereo decoder and audio processor

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TDA7513T

Electrical characteristcs

Table 26. Noise blanker (continued)

Symbol

Parameter

Test condition

Min. Typ. Max. Unit

VRECT

DEV

Deviation dependent Meas. with VMPX =

rectifier Voltage (5)

800mV (75KHz

dev.)

OVD = 11

OVD = 10

OVD = 01

OVD = 00

0.5 0.9 1.3 V

0.9 1.2 1.5 V

1.7 2 2.3 V

2.5 2.8 3.1 V

Fieldstrength

VRECT FS Controlled Rectifier

Voltage (6)

Rectifier Voltage 4)

VMPX = 0mV

VLEVEL << VSBL

(fully mono)

FSC = 11

FSC = 10

FSC = 01

FSC = 00

0.5 0.9 1.3 V

0.9 1.4 1.5 V

1.7 1.9 2.3 V

2.1 2.4 3.1 V

BLT = 00

Î¼s

Suppression Pulse Signal HOLDN

Duration (7)

in Testmode

BLT = 10

BLT = 01

Î¼s

25.5

Î¼s

Noise Rectifier

VRECTADJ discharge

adjustment (8)

Signal PEAK in

Testmode

SRPEAK

Noise Rectifier

Charge

Signal PEAK in

Testmode

Noise Rectifier

Signal PEAK in

VADJMP adjustment through

Multipath (10)

Testmode

BLT = 00

Î¼s

NRD = 00 (8)

(3) 0.3 (3) V/ms

NRD = 01 (8)

(3) 0.8 (3) V/ms

NRD = 10 (8)

(3) 1.3 (3) V/ms

NRD = 11 (8)

(3) 2 (3) V/ms

PCH = 0 (9)

(3) 10 (3) mV/Î¼s

PCH = 1 (9)

(3) 20 (3) mV/Î¼s

MPNB = 00 (10) (3) 0.3 (3) V/ms

MPNB = 00 (10) (3) 0.5 (3) V/ms

MPNB = 00 (10) (3) 0.7 (3) V/ms

MPNB = 00 (10) (3) 0.9 (3) V/ms

1. All thresholds are measured using a pulse with TR =2ms,THIGH = 2ms and TF = 10ms. The repetition rate must not

icrease the PEAK voltage.

2. NBT represents the noiseblanker byte bits D2, D0 for the noise blanker trigger threshold.

3. By design/characterization functionally guaranteed through dedicated test mode structure.

4. NAT represents the noiseblanker byte bit pair D4, D3 for the noise controlled trigger adjustment.

5. OVD represents the noiseblanker byte bit pair D7, D6 for the over deviation detector.

6. FSC represents the fieldstrength byte bit pair D1, D0 for the fieldstrength control.

7. BLT represents the speaker RR byte bit pair D7, D6 for the blanktime adjustment.

8. NRD represents the configuration byte bit pair D1, D0 for the noise rectifier discharge adjustment.

9. PCH represents the stereo decoder byte bit D5 for the noise rectifier charge current adjustment.

10. MPNB represents the highcut byte bit D7 and the field strength byte D7 for the noise rectifier multipath adjustment

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