M58BW016DB Datasheet, PDF (25/69 Pages) STMicroelectronics – 16 Mbit (512 Kb x 32, boot block, burst) 3 V supply Flash memories

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
Bus operations
Table 7. Burst Configuration Register
Bit
Description Value
Description
M15
M14
M13-M11
M10
M9
M8
M7
M6
M5-M4
M3
M2-M0
Read Select
X-Latency⁽¹⁾
Y-Latency⁽²⁾
Valid Data Ready
Burst Type
Valid Clock Edge
Wrapping
Burst Length
0 Synchronous Burst Read
1 Asynchronous Read (default at power-on)
0 Reserved (default value)
000 Reserved (default value)
001 Reserved
010 Reserved
011 5, 5-1-1-1, 5-2-2-2
100 6, 6-1-1-1, 6-2-2-2
101 7, 7-1-1-1, 7-2-2-2
110 8, 8-1-1-1, 8-2-2-2
111 Reserved
0 Reserved (default value)
0 One Burst Clock cycle (default value)
1 Two Burst Clock cycles
0
R valid Low during valid Burst Clock edge (default
value)
1 R valid Low 1 data cycle before valid Burst Clock edge
0 Interleaved (default value)
1 Sequential
0 Falling Burst Clock edge (default value)
1 Rising Burst Clock edge
00 Reserved (default value)
01 Reserved
10 Reserved
11 Reserved
0 Wrap (default value)
1 No wrap
000 Reserved (default value)
001 4 double-words
010 8 double-words
011 Reserved
100 Reserved
101 Reserved
110 Reserved
111 Continuous
1. X latencies can be calculated as: (t_AVQV – t_LLKH + t_QVKH) + t_{SYSTEM MARGIN} < (X -1) t_K. (X is an integer
number from 4 to 8, t_K is the clock period and t_{SYSTEM MARGIN} is the time margin required for the
calculation).
2. Y latencies can be calculated as: t_KHQV + t_{SYSTEM MARGIN} + t_QVKH < Y t_K.
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