M58LT128HST Datasheet, PDF (24/110 Pages) STMicroelectronics – 128-Mbit (8 Mb ×16, Multiple Bank, Multilevel interface, Burst) 1.8 V supply, Secure Flash memories

Command interface
M58LT128HST, M58LT128HSB
4.10
4.10.1
Buffer Enhanced Factory Program command
The Buffer Enhanced Factory Program command has been specially developed to speed up
programming in manufacturing environments where the programming time is critical.
It is used to program one or more Write Buffer(s) of 32 words to a block. Once the device
enters Buffer Enhanced Factory Program mode, the Write Buffer can be reloaded any
number of times as long as the address remains within the same block. Only one block can
be programmed at a time.
If the block being programmed is protected, then the Program operation will abort, the data
in the block will not be changed and the Status Register will output the error.
The use of the Buffer Enhanced Factory Program command requires certain operating
conditions:
● V_PP must be set to V_PPH
● V_DD must be within operating range
● Ambient temperature T_A must be 30°C ± 10°C
● The targeted block must be unprotected
● The start address must be aligned with the start of a 32 word buffer boundary
● The address must remain the Start Address throughout programming.
Dual operations are not supported during the Buffer Enhanced Factory Program operation
and the command cannot be suspended.
The Buffer Enhanced Factory Program Command consists of three phases: the Setup
Phase, the Program and Verify Phase, and the Exit Phase, Please refer to Table 6: Factory
commands for detail information.
Setup phase
The Buffer Enhanced Factory Program command requires two Bus Write cycles to initiate
the command.
● The first Bus Write cycle sets up the Buffer Enhanced Factory Program command.
● The second Bus Write cycle confirms the command.
After the confirm command is issued, read operations output the contents of the Status
Register. The read Status Register command must not be issued as it will be interpreted as
data to program.
The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready to
proceed to the next phase.
If an error is detected, SR4 goes high (set to ‘1’) and the Buffer Enhanced Factory Program
operation is terminated. See Status Register section for details on the error.
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