M24C16-RBN6P Datasheet, PDF (24/38 Pages) STMicroelectronics – 16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit serial I²C bus EEPROM

DC and AC parameters
M24C16, M24C08, M24C04, M24C02, M24C01
Table 15. AC characteristics at 400 kHz (I²C Fast-mode) (M24Cxx-W, M24Cxx-R,
M24Cxx-F)
Test conditions specified in either Table 6, Table 7 or Table 8 and Table 13
Symbol Alt.
Parameter
Min.⁽¹⁾ Max.⁽¹⁾ Unit
f_C
f_SCL Clock frequency
t_CHCL
t_HIGH Clock pulse width high
t_CLCH
t_QL1QL2(2)
t_LOW
t_F
Clock pulse width low
SDA (out) fall time
t_XH1XH2
t_R Input signal rise time
t_XL1XL2
t_F Input signal fall time
t_DXCX t_SU:DAT Data in set up time
t_CLDX t_HD:DAT Data in hold time
t_CLQX
t_DH Data out hold time
t_CLQV(5)(6) t_AA Clock low to next data valid (access time)
t_CHDL t_SU:STA Start condition setup time
t_DLCL t_HD:STA Start condition hold time
t_CHDH t_SU:STO Stop condition set up time
t_DHDL
t_BUF
Time between Stop condition and next Start
condition
-
400
kHz
600
-
ns
1300
-
ns
20⁽³⁾
120
ns
(4)
(4)
ns
(4)
(4)
ns
100
-
ns
0
-
ns
100
-
ns
200
900
ns
600
-
ns
600
-
ns
600
-
ns
1300
-
ns
t_W
t_WR Write time
-
5
ms
1. All values are referred to V_IL(max) and V_IH(min).
2. Characterized only, not tested in production.
3. With C_L = 10 pF.
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f_C < 400 kHz.
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
6. t_CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3V_CC or
0.7V_CC, assuming that R_bus × C_bus time constant is within the values specified in Figure 5.
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Doc ID 5067 Rev 17