STM32F407ZET6 Datasheet, PDF (23/167 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM

STM32F405xx, STM32F407xx
Description
2.2.15
2.2.16
Power supply supervisor
The power supply supervisor is enabled by holding PDR_ON high.
The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, BOR is always active, and
ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold level is reached,
the option byte loading process starts, either to confirm or modify default thresholds, or to
disable BOR permanently. Three BOR thresholds are available through option bytes.
The device remains in reset mode when V_DD is below a specified threshold, V_POR/PDR or
V_BOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the V_DD/V_DDA power supply and compares it to the V_PVD threshold. An interrupt can be
generated when V_DD/V_DDA drops below the V_PVD threshold and/or when V_DD/V_DDA is higher
than the V_PVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
All packages, except for the LQFP64 and LQFP100, have an internal reset controlled
through the PDR_ON signal.
Voltage regulator
The regulator has eight operating modes:
● Regulator ON/internal reset ON
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
● Regulator ON/internal reset OFF
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
● Regulator OFF/internal reset ON
● Regulator OFF/internal reset OFF
Regulator ON
● Regulator ON/internal reset ON
The regulator ON/internal reset ON mode is always enabled on LQFP64 and LQFP100
package.
On LQFP144 package, this mode is activated by setting PDR_ON to V_DD.
On UFBGA176 package, the internal regulator must be activated by connecting
BYPASS_REG to V_SS, and PDR_ON to V_DD.
On LQFP176 packages, the internal reset must be activated by connecting PDR_ON to
V_DD.
Doc ID 022152 Rev 2
23/167