ST10F276Z5_07 Datasheet, PDF (227/239 Pages) STMicroelectronics – 16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM

ST10F276Z5
Figure 69. SSC slave timing
(1)
1)
SCLK
MRST
t₃₁₀
t₃₁₁
t₃₁₂
(2)
2)
t₃₁₄
t₃₁₃
t₃₁₅
t₃₁₅
t₃₁₆
1st out bit
2nd out bit
t₃₁₇ t₃₁₈
MTSR
1st in bit
2nd in bit
Electrical characteristics
t₃₁₅
Last out bit
t₃₁₇ t₃₁₈
Last in bit
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
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