ST10F276Z5_07 Datasheet, PDF (203/239 Pages) STMicroelectronics – 16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM

ST10F276Z5
Electrical characteristics
23.8.12
Note:
PLL lock/unlock
During normal operation, if the PLL is unlocked for any reason, an interrupt request to the
CPU is generated and the reference clock (oscillator) is automatically disconnected from the
PLL input: In this way, the PLL goes into free-running mode, providing the system with a
backup clock signal (free running frequency F_free). This feature allows to recover from a
crystal failure occurrence without risking to go into an undefined configuration: The system
is provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe
mode.
The path between the reference clock and PLL input can be restored only by a hardware
reset, or by a bidirectional software or watchdog reset event that forces the RSTIN pin low.
The external RC circuit on RSTIN pin must be the right size in order to extend the duration of
the low pulse to grant the PLL to be locked before the level at RSTIN pin is recognized high:
Bidirectional reset internally drives RSTIN pin low for just 1024 TCL (definitely not sufficient
to get the PLL locked starting from free-running mode).
Conditions: V_DD = 5 V ±10%, T_A = –40 / +125 ^oC
Table 99. PLL lock/unlock timing
Symbol
Parameter
Conditions
Value
Unit
Min. Max.
T_PSUP
PLL Start-up time ⁽¹⁾
Stable V_DD and reference clock
–
300
T_LOCK PLL Lock-in time
Stable V_DD and reference clock,
starting from free-running mode
–
µs
250
T_JIT
Single Period Jitter ⁽¹⁾ 6 sigma time period variation
(cycle to cycle = 2 TCL) (peak to peak)
–500 +500 ps
F_free
PLL free running
frequency
Multiplication factors: 3, 4
250
Multiplication factors: 5, 8, 10, 16 ⁵⁰⁰
2000
4000
kHz
1. Not 100% tested, guaranteed by design characterization.
23.8.13
Main oscillator specifications
Conditions: V_DD = 5 V ±10%, T_A = –40 / +125 °C
Table 100. Main oscillator specifications
Symbol
Parameter
Conditions
Min.
Value
Typ.
Unit
Max.
g_m
V_OSC
V_AV
Oscillator transconductance
Oscillation amplitude ⁽¹⁾
Oscillation voltage level ⁽¹⁾
Peak to peak
Sine wave middle
t_STUP Oscillator start-up time ⁽¹⁾
Stable V_DD - crystal
Stable V_DD, resonator
1. Not 100% tested, guaranteed by design characterization
8
17
35 mA/V
–
V_DD – 0.4
–
V
– V_DD / 2 –0.25 –
–
3
4
ms
–
2
3
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