L9658 Datasheet, PDF (22/64 Pages) STMicroelectronics – Analog output available for resistance

Functional description
L9658
4.8.4
Serial data input (MOSI, MOSI_A)
MOSI/MOSI_A input takes data from the master processor while chip select is asserted.
The MSB shall be the first bit of each word/byte received on MOSI/MOSI_A and the LSB
shall be the last bit of each word/byte received. This pin has TTL level compatible input
voltages allowing proper operation with microprocessors using a 3.3 to 5.0 V supply.
4.9
Deployment drivers
The on-chip deployment drivers are designed to deliver 1.2 A (min) at 6.9 V VRES.
Deployment current is be 1.2 A (min) for 2 ms (min). The high side driver survives
deployment with 1.47 A, 35 V at VRES and SQL is shorted to ground for 2.5ms. Minimum
load resistance is 1.7. At the end of a deployment, a deploy success flag is asserted via SPI.
Each VRES and GND connection are used to accommodate 8 loops that can be deployed
simultaneously.
Upon receiving a valid deployment condition, the respective SQH and SQL drivers are
turned on. SQH and SQL drivers are also turned on momentarily during a MOS diagnostic.
Otherwise, SQH and SQL are inactive under any normal, fault, or transient conditions. Upon
a successful deployment of the respective SQH and SQL drivers, a deploy command
success flag is asserted via SPI. Refer to "deployment sequence" figure for the valid
condition and the deploy success flagh timing.
Figure 10. Deployment drivers diagram
spi
por
test
vbuck8
iref
VRES0
SQH0
SQL0
GND0
arm01
VRES1
SQH1
SQL1
GND1
VRES4
SQH4
SQL4
GND4
arm45
VRES5
SQH5
SQL5
GND5
Logic
HSD
Isense
Diagnostic
LSD
Isense
ARM01
HSD
Isense
Diagnostic
LSD
Isense
HSD
Isense
Diagnostic
LSD
Isense
ARM45
HSD
Isense
Diagnostic
LSD
Isense
HSD
Isense
Diagnostic
LSD
Isense
ARM23
HSD
Isense
Diagnostic
LSD
Isense
HSD
Isense
Diagnostic
LSD
Isense
ARM67
HSD
Isense
Diagnostic
LSD
Isense
DEPEN
AOUT
VRES2
SQH2
SQL2
GND2
arm23
VRES3
SQH3
SQL3
GND3
VRES6
SQH6
SQL6
GND6
arm67
VRES7
SQH7
SQL7
GND7
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Doc ID 14219 Rev 3