AN2628 Datasheet, PDF (20/27 Pages) STMicroelectronics – Programming ST10F27x CAN interrupt drivers

Register description
AN2628
A.2 CAN control register
CAN1CR (EF00h),
CAN2CR (EE00h)
15 14 13 12 11 10 9
-
-
-
-
-
-
-
XBUS
Reset Value: 0001h
876543210
-
Test CCE DAR -
EIE SIE IE
Init
RW RW RW
RW RW RW RW
Table 4.
Bit
CAN1CR and CAN2CR registers
Function
Init
IE
SIE
EIE
DAR
CCE
Test
Initialization
’0’: Normal operation.
’1’: Initialization is started.
Module interrupt enable
’0’: Disabled - Module interrupt IRQ_B is always high.
’1’: Enabled - Interrupts will set IRQ_B to LOW. IRQ_B remains low until all pending
interrupts are processed.
Status change interrupt enable
’0’: Disabled - No Status Change Interrupt will be generated.
’1’: Enabled - An interrupt will be generated when a message transfer is successfully
completed or a CAN bus error is detected.
Error interrupt enable
‘0’: Disabled - No error status interrupt will be generated.
‘1’: Enabled - A change in the bits BOff or EWarn in the status register will generate
an interrupt.
Disable automatic retransmission
‘0’: Automatic retransmission of disturbed messages enabled.
‘1’: Automatic retransmission disabled.
Configuration change enable
‘0’: The CPU has no write access to the bit timing register.
‘1’: The CPU has write access to the Bit Timing register (while Init = one).
Test mode enable
‘0’: Normal operation.
‘1’: Test mode.
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