74GTL1655A Datasheet, PDF (2/16 Pages) STMicroelectronics – 16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION

74GTL1655A
controlled by output-enable (OEAB and OEBA),
latch-enable (LEAB and LEBA), and clock (CLK)
inputs. For A-to-B data flow, the devices operate
in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLK is held at
a high or low logic level. If LEAB is low, the A data
is stored in the latch/flip-flop on the low-to-high
transition of CLK. When OEAB is low, the outputs
are active. When OEAB is high, the outputs are in
the high-impedance state. Data flow for B to A is
similar to that of A to B, but uses OEBA, LEBA,
and CLK. The output enable (OE) is used to
disable both ports simultaneously.
Active bus-hold circuitry is provided on the A port
to hold unused or floating data inputs at a valid
logic level. When V_CC is between 0 and 1.5 V, the
device is in the high-impedance state during
power up or power down. However, to ensure the
high-impedance state above 1.5V, OE should be
tied to V_CC through a pull-up resistor; the
minimum value of the resistor is determined by the
current-sinking capability of the driver.
All input and output are equipped with protection
circuits against static discharge, giving them 2KV
ESD immunity and transient excess voltage.
Figure 2: Input And Output Equivalent Circuit
t(s) ^{- Obsolete Product(s) Table 2: Pin Description}
c _{PIN N°}
du _{1, 2}
ro 4, 6, 7, 9, 11, 13, 14, 16
P 17, 19, 20, 22, 23, 25, 27, 29
te 31, 32
33
le_{34, 35}
so 36
b_{37, 38, 40, 42, 43, 45, 46, 48}
O ₄₁
SYMBOL
1OEAB, 1OEBA
1A1 to 1A8
2A1 to 2A8
2OEAB, 2OEBA
OE
2LEBA, 2LEAB
BIAS V_CC
2B8 to 2B1
V_REF
NAME AND FUNCTION
Output Enable Input
Data Inputs/Outputs LVTTL
Data Inputs/Outputs LVTTL
Output Enable Input
Output Enable Input
Latch Enable
Pre-Charge Supply Voltage
Data Inputs/Outputs GTL/GTL+
GTL Voltage Reference Input
49, 51, 52, 54, 55, 56, 58, 59
2A1 to 2A8
Data Inputs/Outputs GTL/GTL+
61
V_ERC
Edge Rate Control
62, 63
1LEBA, 1LEAB
Latch Enable
64
CLK
Clock Input (LOW to HIGH edge triggered)
5, 8, 10, 12, 18, 21, 24, 26, 30,
39, 44, 47, 53, 57, 60
GND
Ground (0V)
3, 15, 28, 50
V_CC
Positive Supply Voltage
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