74GTL1655A Datasheet, PDF (1/16 Pages) STMicroelectronics – 16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION

74GTL1655A
16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS
TRANSCEIVERS WITH LIVE INSERTION
s HIGH SPEED GTL/GTL+ UNIVERSAL
TRANSCEIVER:
t_PD = 4.6 ns (MAX.) A to B at V_CC = 3V
s COMBINES D-TYPE LATCHES AND D-TYPE
FLIP-FLOPS FOR OPERATION IN
TRANSPARENT, LATCHED, OR CLOCKED
MODE
TSSOP
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 3.0V to 3.6V
s SYMMETRICAL OUTPUT IMPEDANCE:
) ^|IOH^{| = I}OL^{=24mA (MIN) at V}CC ^{= 3V (A PORT)}
t(s ^{s OUTPUT IMPEDANCE:}
I_OL = 100mA (MIN) at V_CC = 3V (B PORT)
c _{s HIGH-IMPEDANCE STATE DURING POWER}
du ^{UP AND POWER DOWN up to}
ro ^{VCC=BIASVCC=1.5V PERMITT LIVE}
INSERTION
P _{s B-PORT PRECHARGED BY BIASVCC}
te ^{REDUCE NOISE ON THE LINE DURING}
le ^{LIVE INSERTION}
o ^{s EDGE RATE-CONTROL INPUT}
s _{CONFIGURES THE B-PORT OUTPUT RISE}
b _{AND FALL TIMES}
O _{s BUS HOLD ON DATA INPUTS ELIMINATES}
- _{THE NEED FOR EXTERNAL PULL-UP/}
) _{PULL-DOWN RESISTORS (A PORT)}
t(s ^{s DISTRIBUTED V}CC ^{AND GND PIN}
c CONFIGURATION MINIMIZES HIGH-SPEED
u SWITCHING NOISE IN PARALLEL
d _{COMUNICATIONS}
ro s PIN AND FUNCTION COMPATIBLE WITH
P 74 SERIES 1655
te _DESCRIPTION
le _{The 74GTL1655A devices are 16-bit high-drive}
o _{(100mA), low-output-impedance universal bus}
bs^{transceivers designed for backplane applications.}
O^{The 74GTL1655A devices provide live-insertion}
Table 1: Order Codes
PACKAGE
TSSOP
T&R
74GTL1655ATTR
Figure 1: Pin Connection
capability for backplane applications by tolerating
active signals on the data ports when the devices
are powered off. In addition, a biasing pin
preconditions the GTL/GTL+ port to minimize
disruption to an active backplane.
The edge rate-control (V_ERC) input is provided so
the rise and fall time of the B outputs can be
configured to optimize for various backplane
loading conditions. Data flow in each direction is
October 2004
Rev. 1
1/16