74AC573 Datasheet, PDF (2/11 Pages) STMicroelectronics – OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

74AC573
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2, 3, 4, 5, 6,
7, 8, 9
12, 13, 14,
15, 16, 17,
18, 19
11
10
20
SYMBOL
OE
D0 to D7
NAME AND FUNCTION
Asynchronous Master
Reset (Active LOW)
Data Inputs
Q0 to Q7 3-State Latch Outputs
LE
GND
V_CC
Latch Enable Input
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OE
LE
D
H
X
X
L
L
X
L
H
L
L
H
H
X : Don’t Care
Z : High Impedance
NOTE: Outputs are latched at the time when the input is taken LOW logic level
LOGIC DIAGRAM
OUTPUT
Q
Z
NO CHANGE
L
H
This logic diagram has not be used to estimate propagation delays
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