74AC573 Datasheet, PDF (1/11 Pages) STMicroelectronics – OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

74AC573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS (NON INVERTED)
s HIGH SPEED: t_PD = 4.5ns (TYP.) at V_CC = 5V
s LOW POWER DISSIPATION:
I_CC = 4µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28 % V_CC (MIN.)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74AC573 is an advanced high-speed CMOS
OCTAL D-TYPE LATCH with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C²MOS
technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74AC573B
74AC573M
T&R
74AC573MTR
74AC573TTR
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched at the logic level of D input data. While the
(OE) input is low, the 8 outputs will be in a normal
logic state (high or low logic level); while OE is in
high level, the outputs will be in a high impedance
state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
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