M24C02-DRE Datasheet, PDF (19/41 Pages) STMicroelectronics – 2-Kbit serial IC bus EEPROM - 105C operation

M24C02-DRE
Instructions
4.1.5
Minimizing Write delays by polling on ACK
The maximum Write time (t_w) is shown in AC characteristics tables in Section 8: DC and AC
parameters, but the typical time is shorter. To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 7, is:
• Initial condition: a Write cycle is in progress.
• Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
• Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 7. Write cycle polling flowchart using ACK
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DocID027420 Rev 1
19/41