TDA7580 Datasheet, PDF (18/31 Pages) STMicroelectronics – FM/AM DIGITAL IF SAMPLING PROCESSOR

TDA7580
SPI INTERFACE
Figure 8. SPI Timings
SS
MISO
MOSI
SCL
(CPOL=0,CPHA=0)
Valid
Valid
t_setup
t_dtr
t_sssetup
t_sclkl
t_hold
t_sshold
t_sclkh
t_sclk
Symbol
T_DSP
t_sclk
t_dtr
t_setup
t_hold
t_sclkh
t_sclkl
t_sssetup
t_sshold
t_sclk
t_dtr
t_setup
t_hold
t_sclkh
Description
Internal DSP Clock Period (Typical 1/74.1MHz)
MASTER
Minimum Clock Cycle
Minimum Sclk edge to MOSI valid
Minimum MISO setup time
Minimum MISO hold time
Minimum SCK high time
Minimum SCK low time
Minimum SS setup time
Minimum SS hold time
SLAVE
Minimum Clock Cycle
Minimum Sclk edge to MOSI valid
Minimum MOSI setup time
Minimum MOSI hold time
Minimum SCK high time
Value
13.495
12*T_DSP
40
16
9
0.5*t_sclk
0.5*t_sclk
40
25
12*T_DSP
40
16
9
0.5*t_sclk
18/31
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns