MK68564 Datasheet, PDF (18/46 Pages) STMicroelectronics – SERIAL INPUT OUTPUT

MK68564
character is loaded into the transmit buffer before
enabling the transmitter, that character will be sent
in place of the sync character(s).
Start of Transmission. Transmission will begin
with the loading of the first data character into the
transmit buffer, if the transmitter is already enabled.
For CRC to be calculated correctly on each mes-
sage, the CRC generator must be reset to all zeros
before the first data character is loaded into the
transmit buffer. This is accomplished by issuing a
Reset Tx CRC Generator command in the
Command Register.
Synchronous Transmit Characteristics. In all
Synchronous modes, characters are sent with the
least-significant bits first. All data is shifted out of the
Transmit Data pin (TxD) on the falling edge of the
Transmit Clock (TxC). The transmitter can transmit
from one to eight data bits per character. This re-
quires right-hand justification of data written to the
transmit buffer, if the selected word length is less
than eight bits per character. When the programmed
Figure 11a : External Sync Timing.
character length is six or seven bits, the unused bits
in the transmit buffer are ignored. If a word length of
five bits per character or less is selected, the data
loaded into the transmit buffer must be formatted as
described in the Transmit Control register part of the
Register Description section.
The number of bits per character to be transmitted
can be changed on the fly. Any data written to the
transmit buffer, after the bits per character field is
changed, are affected by the change. The same is
true of any characters in the buffer at the time the
bits per character field is changed. The change in
the number of bits per character does not affect the
character in the process of being shifted out.
A transmitted message can be terminated by CRC
and sync characters, by sync characters only, or by
pad characters (replacing the sync character(s) in
the Sync Word Registers with pad characters). How
a message is terminated is controlled by the Tx Un-
derrun/EOM latch in Status Register 0.
Figure 11b : Simple External Sync Delay.
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