MK68564 Datasheet, PDF (1/46 Pages) STMicroelectronics – SERIAL INPUT OUTPUT

MK68564
. COMPATIBLE WITH MK68000 CPU
. COMPATIBLE WITH MK68000 SERIES DMA’s
. TWO INDEPENDENT FULL-DUPLEX CHAN-
NELS
. TWO INDEPENDENT BAUD-RATE GENER-
ATORS
- ^{Crystal oscillator input}
- ^{Single-phase TTL clock input}
. DIRECTLY ADDRESSABLE REGISTERS
(all control registers are read/write)
. DATA RATE IN SYNCHRONOUS OR ASYN-
CHRONOUS MODES
.. - 0-1.25M bits/second with 5.0MHz system
clock rate
SELF-TEST CAPABILITY
RECEIVE DATA REGISTERS ARE QUADRU-
. PLY BUFFERED ; TRANSMIT REGISTERS
ARE DOUBLY BUFFERED
DAISY-CHAIN PRIORITY INTERRUPT LOGIC
PROVIDES AUTOMATIC INTERRUPT VECTO-
RING WITHOUT EXTERNAL LOGIC
. MODEM STATUS CAN BE MONITORED
- ^{Separate modem controls for each channel}
. ASYNCHRONOUS FEATURES
- ^{5, 6, 7, or 8 bits/character}
- ^{1, 11/2, or 2 stop bits}
- ^{Even, odd, or no parity}
- ^{x1, x16, x32, and x64 clock modes}
. - Break generation and detection
- ^{Parity, overrun, and framing error detection}
BYTE SYNCHRONOUS FEATURES
- ^{Internal or external character synchronization}
- ^{One or two sync characters in separate regis-}
ters
- ^{Automatic sync character insertion}
. - CDC-16 or CRC-CCITT block check genera-
tion and checking
BIT SYNCHRONOUS FEATURES
- ^{Abort sequence generation and detection}
- ^{Automatic zero insertion and deletion}
- ^{Automatic flag insertion between messages}
- ^{Address field recognition}
- ^{I-field residue handling}
- ^{Valid receive messages protected from over-}
run
- ^{CRC-16 or CRC-CCITT block check genera-}
tion and checking
SERIAL INPUT OUTPUT
1
PDIP48
(Plastic Package)
PLCC52
(Chip Carrier)
DESCRIPTION
The MK68564 SIO (Serial Input Output) is a dual-
channel, multi-function peripheral circuit, designed
to satisfy a wide variety of serial data communica-
tions requirements in microcomputer systems. Its
basic function is a serial-to-parallel, parallel-to-serial
converter/controller ; however within that role, it is
systems software configurable so that its ”persona-
lity” may be optimized for any given serial data
communications application.
The MK68564 is capable of handling asynchronous
protocols, synchronous byte-oriented protocols
(such as IBM Bisync), and synchronous bit-oriented
protocols (such as HDLC and IBM SDLC). This ver-
satile device can also be used to support virtually
any serial protocol for applications other than data
communications (cassette or floppy disk interface,
for example).
The MK68564 can generate and check CRC codes
in any synchronous mode and may be programmed
to check data integrity in various modes. The device
also has facilities for modem controls in each chan-
nel. In applications where these controls are not
needed, the modem controls may be used for gene-
ral-purpose I/O.
January 1989
1/46