VL6524 Datasheet, PDF (17/70 Pages) STMicroelectronics – VGA single-chip camera module

VL6524/VS6524
Clock control
Similarly when using sub-sampled output modes the PCLK frequency is not reduced but
instead pairs of PCLKs are 'dropped', see Section 6.1.2: Subsampling module for details.
The PCLK edge used to qualify the output data is fully programmable. It is also possible to
program the state of the PCLK line (high or low) for the times when it is inactive.
5.4
PCLK gating
By default the PCLK output from the VL6524/VS6524 is not continuous. The PCLK qualifies
all video data (and embedded codes if selected) on each video line and each interframe line
but does not qualify the interline blanking data. In non-subsampled modes the PCLK is
continuous during the video data output. The operation of the PCLK can be controlled using
the bPClkSetup register (Table 29).
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