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STM32F217ZGT6 Datasheet, PDF (166/173 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, crypto, ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, crypto,
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Revision history
STM32F21xxx
Table 92. Document revision history (continued)
Date
Revision
Changes
22-Apr-2011
Updated tres(TIM) in Table 47: Characteristics of TIMx connected to the
APB1 domain. Modified tres(TIM) and fEXT Table 48: Characteristics of
TIMx connected to the APB2 domain.
Changed tw(SCKH) to tw(SCLH), tw(SCKL) to tw(SCLL), tr(SCK) to tr(SCL), and
tf(SCK) to tf(SCL) in Table 49: I2C characteristics and Figure 37: I2C bus
AC waveforms and measurement circuit.
Added Table 54: USB OTG FS DC electrical characteristics and
updated Table 55: USB OTG FS electrical characteristics.
Updated VDD minimum value in Table 59: Ethernet DC electrical
characteristics.
Updated Table 63: ADC characteristics and RAIN equation.
Updated RAIN equation. Updated Table 65: DAC characteristics.
Updated tSTART in Table 66: TS characteristics.
Updated Table 68: Embedded internal reference voltage.
Modified FSMC_NOE waveform in Figure 53: Asynchronous non-
multiplexed SRAM/PSRAM/NOR read waveforms. Shifted end of
FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK
period, changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-
AIV), td(CLKH-NOEH) to td(CLKL-NOEH), and td(CLKH-NWEH) to td(CLKL-
4
NWEH), and updated data latency from 1 to 0 in Figure 57:
(continued) Synchronous multiplexed NOR/PSRAM read timings, Figure 58:
Synchronous multiplexed PSRAM write timings, Figure 59:
Synchronous non-multiplexed NOR/PSRAM read timings, and
Figure 60: Synchronous non-multiplexed PSRAM write timings,
Changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-AIV),
td(CLKH-NOEH) to td(CLKL-NOEH), td(CLKH-NWEH) to td(CLKL-NWEH), and
modified tw(CLK) minimum value in Table 73, Table 74, Table 75, and
Table 76.
Updated R typical value in Table 67: VBAT monitoring
characteristics.Updated note 2 in Table 69, Table 70, Table 71,
Table 72, Table 73, Table 74, Table 75, and Table 76.
Modified th(NIOWR-D) in Figure 66: PC Card/CompactFlash controller
waveforms for I/O space write access.
Modified FSMC_NCEx signal in Figure 67: NAND controller
waveforms for read access, Figure 68: NAND controller waveforms for
write access, Figure 69: NAND controller waveforms for common
memory read access, and Figure 70: NAND controller waveforms for
common memory write access.
Specified Full speed (FS) mode for Figure 86: USB OTG HS
peripheral-only connection in FS mode and Figure 87: USB OTG HS
host-only connection in FS mode.
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Doc ID 17050 Rev 8
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