STM32F217ZGT6 Datasheet, PDF (124/173 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, crypto, ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, crypto,

Electrical characteristics
STM32F21xxx
Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
FSMC_NEx
t_w(NE)
FSMC_NOE
FSMC_NWE
FSMC_A[25:0]
FSMC_NBL[1:0]
FSMC_D[15:0]
FSMC_NADV⁽¹⁾
t_{v(NWE_NE)}
t_w(NWE)
t_{v(A_NE)}
t_{v(BL_NE)}
t_{v(Data_NE)}
t _{v(NADV_NE)}
t_w(NADV)
t_{h(A_NWE)}
Address
t_{h(BL_NWE)}
NBL
t_{h(Data_NWE)}
Data
t _{h(NE_NWE)}
ai14990
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings⁽¹⁾⁽²⁾
Symbol
Parameter
Min
Max
Unit
t_w(NE)
FSMC_NE low time
3T_HCLK
3T_HCLK+ 4
ns
t_{v(NWE_NE}) FSMC_NEx low to FSMC_NWE low
T_HCLK– 0.5 T_HCLK+ 0.5
ns
t_w(NWE) FSMC_NWE low time
T_HCLK– 0.5 T_HCLK+ 3
ns
t_{h(NE_NWE)}
FSMC_NWE high to FSMC_NE high hold
time
T_HCLK
-
ns
t_{v(A_NE)} FSMC_NEx low to FSMC_A valid
-
0
ns
t_{h(A_NWE)} Address hold time after FSMC_NWE high T_HCLK- 3
-
ns
t_{v(BL_NE)} FSMC_NEx low to FSMC_BL valid
-
0.5
ns
t_{h(BL_NWE)}
FSMC_BL hold time after FSMC_NWE
high
T_HCLK– 1
-
ns
t_{v(Data_NE)} Data to FSMC_NEx low to Data valid
-
T_HCLK+ 5
ns
t_{h(Data_NWE)} Data hold time after FSMC_NWE high
T_HCLK+0.5
-
ns
t_{v(NADV_NE)} FSMC_NEx low to FSMC_NADV low
-
2
ns
t_w(NADV) FSMC_NADV low time
-
T_HCLK+ 1.5
ns
1. C_L = 30 pF.
2. Based on characterization, not tested in production.
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