ST10F273E Datasheet, PDF (163/179 Pages) STMicroelectronics – 16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM

ST10F273E
Electrical characteristics
Table 78. Demultiplexed bus timings (continued)
Symbol
Parameter
F_CPU = 40 MHz
TCL = 12.5 ns
Min.
Max.
Variable CPU Clock
1/2 TCL = 1 to 64 MHz
Min.
Max.
t₃₉
SR
Latched CS low to Valid
Data in
–
16.5 + t_C + 2t_A
–
3TCL – 21 + t_C + 2t_A ns
t₄₁
CC
Latched CS hold after RD,
WR
2 + t_F
–
TCL – 10.5 + t_F
–
ns
t₈₂
CC
Address setup to RdCS,
WrCS (with RW-delay)
14 + 2t_A
–
2TCL – 11 + 2t_A
–
ns
t₈₃
CC
Address setup to RdCS,
WrCS (no RW-delay)
2 + 2t_A
–
TCL –10.5 + 2t_A
–
ns
t₄₆
SR
RdCS to Valid Data in
(with RW-delay)
–
4 + t_C
–
2TCL – 21 + t_C
ns
t₄₇
SR
RdCS to Valid Data in
(no RW-delay)
–
16.5 + t_C
–
3TCL – 21 + t_C
ns
t₄₈
CC
RdCS, WrCS Low Time
(with RW-delay)
15.5 + t_C
–
2TCL – 9.5 + t_C
–
ns
t₄₉
CC
RdCS, WrCS Low Time
(no RW-delay)
28 + t_C
–
3TCL – 9.5 + t_C
–
ns
t₅₀ CC Data valid to WrCS
t₅₁ SR Data hold after RdCS
t₅₃
SR
Data float after RdCS
(with RW-delay) ³
10 + t_C
0
–
–
–
16.5 + t_F
2TCL – 15 + t_C
–
ns
0
–
ns
–
2TCL – 8.5 + t_F ns
t₆₈
SR
Data float after RdCS
(no RW-delay) ³
–
4 + t_F
–
TCL – 8.5 + t_F
ns
t₅₅
CC
Address hold after
RdCS, WrCS
– 8.5 + t_F
–
– 8.5 + t_F
–
ns
t₅₇ CC Data hold after WrCS
2 + t_F
–
TCL – 10.5 + t_F
–
ns
1. RW-delay and t_A refer to the next following bus cycle
2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore
address changes before the end of RD have no impact on read cycles.
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