ST72321J Datasheet, PDF (160/179 Pages) STMicroelectronics – 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 5 TIMERS, SPI, SCI, I2C INTERFACE

ST72321J
12.11 COMMUNICATION INTERFACE CHARACTERISTICS
12.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V_DD,
f_CPU, and T_A unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Symbol
Parameter
f_SCK
1/t_c(SCK)
SPI clock frequency
t_r(SCK)
t_f(SCK)
t_su(SS)
t_h(SS)
t_w(SCKH)
t_w(SCKL)
t_su(MI)
t_su(SI)
t_h(MI)
t_h(SI)
t_a(SO)
t_dis(SO)
t_v(SO)
t_h(SO)
t_v(MO)
t_h(MO)
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Master
Slave
Conditions
f_CPU=8MHz
f_CPU=8MHz
Min
f_CPU/128
0.0625
0
Max
f_CPU/4
2
f_CPU/2
4
Unit
MHz
see I/O port pin description
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (before capture edge)
120
120
100
90
100
100
100
ns
100
0
120
240
90
0
0.25
0.25
t_CPU
Figure 97. SPI Slave Timing Diagram with CPHA=0 ³⁾
SS _INPUT
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t_su(SS)
t_a(SO)
MISO _OUTPUT
see note 2
t_su(SI)
t_c(SCK)
tt_{ww((SSCCKKHL))}
t_v(SO)
MSB OUT
t_h(SI)
BIT6 OUT
t_h(SS)
t_h(SO)
t_r(SCK)
t_f(SCK)
LSB OUT
t_dis(SO)
see
note 2
MOSI _INPUT
MSB IN
BIT1 IN
LSB IN
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV_DD and 0.7xV_DD.
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