STW4510 Datasheet, PDF (16/57 Pages) STMicroelectronics – 2 step-down DC/DC converters / 5 LDO power management

Functional description
Figure 3. Switching from high power mode to sleep/Vsdc1_OFF mode
STw4510
PWREN
HPM
VddOK
Clock32K_in
Pdn_regulator
(int. signal)
Internal_osc
SLEEP / OFF controlled by PWREN
HPM
Vana[i] & Vmmc
controlled by I2C _{Vana[i] in SLEEP mode (low current capability)}
Voutputs _{Vsdc2 @ 1.8V}
) _STw4510
ct(s _{Vdig @ 1.2V}
u _{Vsdc1 @ 1.2V}
Prod _t0
Vmmc not affected by sleep mode
Vsdc2 @ 1.8V in SLEEP mode (low
current capability)
Vdig @ 1.2V still active
Vsdc1 in OFF state
Vsdc2 @ 1.8V
Vdig @ 1.2V still active
Vsdc1 @ 1.2V,
available after
stabilization time
1ms max
Obsolete ^{Product(s) - Obsolete 3.2.2}
PM00128
POWER OFF / VddOK
● In case of VddOK falling edge (under voltage on Vsdc1, Vsdc2 detected), the
processor is reset (Res_pro low during 1.8 ms minimum) and started again with no
time-out. (See Figure 4)
● In case of VddOK falling down edge (under Pwren falling edge) the processor is not
reset (Res_pro keeps its high level)
● In case of Pon falling edge (switch off of STw4510 from the main processor), the
processor is also reset with no time-out. It is considered that clean switch off between
modem and processor is done by software directly.
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