STM32F415XX Datasheet, PDF (153/186 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM

STM32F415xx, STM32F417xx
Electrical characteristics
Table 84. Switching characteristics for PC Card/CF read and write cycles
in I/O space⁽¹⁾⁽²⁾
Symbol
Parameter
Min
Max
t_w(NIOWR)
FSMC_NIOWR low width
t_v(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid
t_h(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid
t_{d(NCE4_1-NIOWR)} FSMC_NCE4_1 low to FSMC_NIOWR valid
t_{h(NCEx-NIOWR)} FSMC_NCEx high to FSMC_NIOWR invalid
t_{d(NIORD-NCEx)} FSMC_NCEx low to FSMC_NIORD valid
t_{h(NCEx-NIORD)} FSMC_NCEx high to FSMC_NIORD) valid
t_w(NIORD)
FSMC_NIORD low width
t_su(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high
t_d(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high
1. C_L = 30 pF.
2. Based on characterization, not tested in production.
8T_HCLK –1
-
8T_HCLK– 2
-
5T_HCLK–1.5
-
5T_HCLK– 1.5
8T_HCLK–0.5
9
0
-
5T_HCLK– 1
-
5T_HCLK+ 2.5
-
5T_HCLK+ 2
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NAND controller waveforms and timings
Figure 69 through Figure 72 represent synchronous waveforms, and Table 85 and Table 86
provide the corresponding timings. The results shown in this table are obtained with the
following FSMC configuration:
• COM.FSMC_SetupTime = 0x01;
• COM.FSMC_WaitSetupTime = 0x03;
• COM.FSMC_HoldSetupTime = 0x02;
• COM.FSMC_HiZSetupTime = 0x01;
• ATT.FSMC_SetupTime = 0x01;
• ATT.FSMC_WaitSetupTime = 0x03;
• ATT.FSMC_HoldSetupTime = 0x02;
• ATT.FSMC_HiZSetupTime = 0x01;
• Bank = FSMC_Bank_NAND;
• MemoryDataWidth = FSMC_MemoryDataWidth_16b;
• ECC = FSMC_ECC_Enable;
• ECCPageSize = FSMC_ECCPageSize_512Bytes;
• TCLRSetupTime = 0;
• TARSetupTime = 0.
In all timing tables, the T_HCLK is the HCLK clock period.
DocID022063 Rev 4
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