STM32F050C6T6A Datasheet, PDF (15/97 Pages) STMicroelectronics – Low- and medium-density advanced ARM-based 32-bit MCU with up to 32 Kbytes Flash, timers, ADC and comm. interfaces

STM32F050xx
Functional overview
3.6
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
Figure 2. Clock tree
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Doc ID 023683 Rev 1
15/97