STDVE001A Datasheet, PDF (15/49 Pages) STMicroelectronics – Adaptive single 3.4 Gbps TMDS/HDMI signal equalizer

STDVE001A
Functional description
TMDS voltage levels
The TMDS interface standard is a signaling method intended for point-to-point
communication over a tightly controlled impedance medium. The TMDS standard uses a
lower voltage swing than other common communication standards, achieving higher data
rates with reduced power consumption while reducing EMI emissions and system
susceptibility to noise. The device is capable of detecting differential signals as low as
100 mV within the entire common mode voltage range.
3.2
Operating modes
Table 4.
OE_N
OE_N operating modes
Input
IN+
IN-
Output
OUT+ OUT-
Function
L
H
L
L
H
X
L
H
L
Active mode
H
L
H
Active mode
X
Hi-Z Hi-Z Low power mode
The OE_N input activates a hardware power down mode. When the power down mode is
active (OE_N = H), all input and output buffers and internal bias circuitry are powered-off
and disabled.
Outputs are tri-stated in power-down mode. When exiting power-down mode, there is a
delay associated with turning on band-references and input/output buffer circuits.
Note that the OE_N pin is only used to disable the TMDS paths in the chip to same
maximum amount of current. It does not affect the HPD, DDC and CEC portions. The DDC
is controlled only by the DDC_EN pin whereas the HPD and CEC are always active as long
as the supply to the chip is present.
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