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ST10F269 Datasheet, PDF (141/160 Pages) STMicroelectronics – 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM
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ST10F269
21.4.10 - Multiplexed Bus
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF,
ALE cycle time = 6 TCL + 2tA + tC + tF (75ns at 40MHz CPU clock without wait states).
Table 35 : Multiplexed Bus Characteristics
Symbol
Parameter
Max. CPU Clock
= 40MHz
min.
max.
Variable CPU Clock
1/2 TCL = 1 to 40MHz
min.
max.
t5
CC ALE high time
4 + tA
–
TCL - 8.5 + tA
–
ns
t6
CC Address setup to ALE
2 + tA
–
TCL - 10.5 + tA
–
ns
t7
CC Address hold after ALE
1 4 + tA
–
TCL - 8.5 + tA
–
ns
t8
CC ALE falling edge to RD, WR
4 + tA
–
TCL - 8.5 + tA
(with RW-delay)
–
ns
t9
CC ALE falling edge to RD, WR (no -8.5 + tA
–
RW-delay)
-8.5 + tA
–
ns
t10 CC Address float after RD, WR
–
6
–
(with RW-delay)
1
6
ns
t11 CC Address float after RD, WR
–
18.5
–
(no RW-delay)
1
TCL + 6
ns
t12 CC RD, WR low time
(with RW-delay)
15.5 + tC
–
2 TCL -9.5 + tC
–
ns
t13 CC RD, WR low time
(no RW-delay)
28 + tC
–
3 TCL -9.5 + tC
–
ns
t14 SR RD to valid data in
(with RW-delay)
–
6 + tC
–
2 TCL - 19 + tC ns
t15 SR RD to valid data in
(no RW-delay)
–
18.5 + tC
–
3 TCL - 19 + tC ns
t16 SR ALE low to valid data in
–
18.5
–
+ tA + tC
3 TCL - 19
ns
+ tA + tC
t17 SR Address/Unlatched CS to valid
–
22 + 2tA +
–
data in
tC
4 TCL - 28
ns
+ 2tA + tC
t18 SR Data hold after RD
rising edge
0
–
0
–
ns
t19 SR Data float after RD
1
–
16.5 + tF
–
2 TCL - 8.5 + tF ns
t22 CC Data valid to WR
10 + tC
–
2 TCL -15 + tC
–
ns
t23 CC Data hold after WR
4 + tF
–
2 TCL - 8.5 + tF
–
ns
t25 CC ALE rising edge after RD, WR 15 + tF
–
2 TCL -10 + tF
–
ns
t27 CC Address/Unlatched CS hold
10 + tF
–
2 TCL -15 + tF
after RD, WR
–
ns
t38 CC ALE falling edge to Latched CS -4 - tA
10 - tA
-4 - tA
10 - tA
ns
t39 SR Latched CS low to Valid Data In
–
18.5 + tC +
–
2tA
3 TCL - 19
ns
+ tC + 2tA
t40 CC Latched CS hold after RD, WR 27 + tF
–
3 TCL - 10.5 + tF
–
ns
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