M65KA128AL Datasheet, PDF (14/53 Pages) STMicroelectronics – 128Mbit (4 Banks x 2M x 16) 1.8V Supply, Low Power SDRAMs

Operations
M65KA128AL
3.7
Deep Power-Down
The purpose of this mode is to achieve maximum power reduction by cutting the power
supply to the whole memory array. Data is no longer retained when the device enters Deep
Power-Down Mode.
The Low Power SDRAM is switched to Deep Power-Down mode by applying V_IL to E and W,
and V_IH to RAS and CAS on the rising edge of the clock, K, and by driving KE Low, V_IL. For
more information, see Figure 25: Deep Power-Down Entry AC Waveforms.
The Low Power SDRAM is released from Deep Power-Down mode by applying V_IH to KE,
with all other pins Don’t Care. Then a special sequence, is required before the device can
take any new command into account:
1. Maintain No Operation status conditions (see Table 3 for a minimum time of 200µs,
2. Issue a Precharge command to all the banks of the device (see Section 4.6: Precharge
command for details),
3. Issue 2 or more Auto-Refresh commands,
4. Issue a Mode Register Set command and an Extended Mode Register Set command to
initialize the Mode Register and the Extended Mode Register, respectively.
The third and fourth steps can be swapped.
The Deep Power-Down mode exit sequence is illustrated in Figure 26: Deep Power-Down
Exit AC Waveforms.
Table 2. Operating Modes ⁽¹⁾
Operating Mode KEn-1 KEn E RAS CAS W A10 A9, A11 A0-A7 BA0-BA1
Burst Read
V_IH
Burst Write
V_IH
Self Refresh
V_IH
Auto Refresh
V_IH
Power-Down
V_IH
Deep Power-Down V_IH
Device Deselect
V_IH
No Operation
V_IH
1. X = Don’t Care V_IL or V_IH.
X
V_IL
V_IH
X
V_IL
V_IH
V_IL
V_IL
V_IL
V_IH
V_IL
V_IL
V_IL
V_IH
V_IL
V_IH
X
V_IL
V_IL
V_IH
X
V_IH
X
X
V_IL
V_IH
V_IL V_IH V_IL
V_IL
V_IL V_IL
V_IL V_IH
V_IL V_IH
V_IH V_IH
X
X
V_IH
V_IL
X
XX
V_IH V_IH
Valid
Valid
X
X
Start
Column Bank Select
Address
Start
Column Bank Select
Address
X
X
X
X
X
X
X
X
X
X
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