M58LW064C Datasheet, PDF (14/61 Pages) STMicroelectronics – 64 Mbit (4Mb x16, Uniform Block, Burst) 3V Supply Flash Memory

M58LW064C
put Enable must remain High, V_IH, during the
whole Asynchronous Bus Write operation. See
Figures 15 and 17 Asynchronous Latch Controlled
Write AC Waveforms, and Tables 19 and 20,
Asynchronous Write and Latch Controlled Write
AC Characteristics, for details of the timing re-
quirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when the Output Enable
is High.
Standby. When Chip Enable is High, V_IH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high imped-
ance state regardless of Output Enable or Write
Enable. The Supply Current is reduced to the
Standby Supply Current, I_DD1.
During Program or Erase operations the memory
will continue to use the Program/Erase Supply
Current, I_DD3, for Program or Erase operations un-
til the operation completes.
Automatic Low Power. If there is no change in
the state of the bus for a short period of time during
Asynchronous Bus Read operations the memory
enters Auto Low Power mode where the internal
Supply Current is reduced to the Auto-Standby
Supply Current, I_DD5. The Data Inputs/Outputs will
still output data if a Bus Read operation is in
progress.
Automatic Low Power is only available in Asyn-
chronous Read modes.
Power-Down. The memory is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
power consumption is reduced to the Power-Down
level, I_DD2, and the outputs are high impedance,
independent of Chip Enable, Output Enable or
Write Enable.
Table 2. Asynchronous Bus Operations
Bus Operation
Step
Asynchronous Bus Read
Asynchronous Latch
Controlled Bus Read
Address Latch
Read
Asynchronous Page Read
Asynchronous Bus Write
Asynchronous Latch
Controlled Bus Write
Address Latch
Output Disable
Standby
Power-Down
Note: 1. X = Don’t Care V_IL or V_IH. High = V_IH or V_HH.
E G W RP L
V_IL V_IL V_IH High V_IL
V_IL V_IL V_IH High V_IL
V_IL V_IL V_IH High V_IH
V_IL V_IL V_IH High V_IL
V_IL V_IH V_IL High V_IL
V_IL V_IH V_IL High V_IL
V_IL V_IH V_IH High X
V_IH X
X High X
X
X
X VIL X
A1-A22
Address
Address
X
Address
Address
Address
X
X
X
DQ0-DQ15
Data Output
High Z
Data Output
Data Output
Data Input
Data Input
High Z
High Z
High Z
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