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| ST72324JX Datasheet, PDF (133/164 Pages) STMicroelectronics – 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH,10-BIT ADC, 4 TIMERS,SPI,SCI INTERFACE | |||
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ST72324Jx ST72324Kx
12.9 I/O PORT PIN CHARACTERISTICS
12.9.1 General Characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
VIL
Input low level voltage (standard voltage
devices)1)
VIH Input high level voltage 1)
Vhys Schmitt trigger voltage hysteresis 2)
0.7xVDD
0.7
IINJ(PIN)3)
Injected Current on Flash device pin PB0
Injected Current on other I/O pins
VDD=5V
0
ΣIINJ(PIN)3)
Total injected current (sum of all I/O and
control pins)
Ilkg Input leakage current
VSS ⤠VIN ⤠VDD
IS
Static current consumption induced by each
floating input pin
Floating input mode4)
200
RPU Weak pull-up equivalent resistor 5)
VIN=VSS VDD=5V
50
120
CIO I/O pin capacitance
5
tf(IO)out Output high to low level fall time 1)
CL=50pF
25
tr(IO)out Output low to high level rise time 1)
Between 10% and
90%
25
tw(IT)in External interrupt pulse time 6)
1
0.3xVDD
V
V
+4
±4
mA
±25
±1
µA
250
kâ¦
pF
ns
tCPU
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specifica-
tion. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. Refer to Section 12.2.2
on page 117 for more details.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example and leaving the I/O unconnected on the board or an external pull-up or pull-down resistor (see Figure 69). Data
based on design simulation and/or technology characteristics, not tested in production.
5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-
scribed in Figure 70).
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 69. Unused I/O Pins configured as input
VDD
ST7XXX
10k⦠UNUSED I/O PORT
10kâ¦
UNUSED I/O PORT
ST7XXX
Note: I/O can be left unconnected if it is configured as output
(0 or 1) by the software. This has the advantage of
greater EMC robustness and lower cost.
Figure 70. Typical IPU vs. VDD with VIN=VSS
90
80
Ta= 1 40°C
Ta= 9 5°C
70
Ta= 2 5°C
60
Ta=-45 °C
50
40
30
20
10
0
2 2 .5 3 3 .5 4 4 .5 5 5 .5 6
V dd (V )
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