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ST72324JX Datasheet, PDF (117/164 Pages) STMicroelectronics – 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH,10-BIT ADC, 4 TIMERS,SPI,SCI INTERFACE
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ST72324Jx ST72324Kx
12.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
12.2.1 Voltage Characteristics
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
Symbol
Ratings
VDD - VSS
VPP - VSS
VIN 1) & 2)
Supply voltage
Programming Voltage
Input Voltage on true open drain pin
Input voltage on any other pin
|∆VDDx| and |∆VSSx| Variations between different digital power pins
|VSSA - VSSx|
Variations between digital and analog ground pins
VESD(HBM)
Electro-static discharge voltage (Human Body Model)
VESD(MM)
Electro-static discharge voltage (Machine Model)
12.2.2 Current Characteristics
Maximum value
6.5
13
VSS-0.3 to 6.5
VSS-0.3 to VDD+0.3
50
50
Unit
V
mV
see Section 12.8.3 on page 132
Symbol
Ratings
Maximum value
Unit
IVDD
Total current into VDD power lines
(source) 3)
32-pin devices
44-pin devices
75
150
mA
IVSS
Total current out of VSS ground lines
(sink) 3)
32-pin devices
44-pin devices
75
150
mA
Output current sunk by any standard I/O and control pin
25
IIO
Output current sunk by any high sink I/O pin
50
Output current source by any I/Os and control pin
- 25
Injected current on VPP pin
±5
Injected current on RESET pin
±5
mA
IINJ(PIN) 2) & 4)
Injected current on OSC1 and OSC2 pins
±5
Injected current on Flash device pin PB0
+5
Injected current on any other pin 5) & 6)
±5
ΣIINJ(PIN) 2)
Total injected current (sum of all I/O and control pins) 5)
± 25
Notes:
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD or VSS.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be
respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD
while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the
corresponding VIN maximum must always be respected
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. Negative injection disturbs the analog performance of the device. See note in “ADC Accuracy” on page 145.
For best reliability, it is recommended to avoid negative injection of more than 1.6mA.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive
and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi-
mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.
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