SPEAR-09-H042 Datasheet, PDF (13/16 Pages) STMicroelectronics – SPEAr™ Head200, ARM 926, 200 K customizable eASIC™ gates, large IP portfolio SoC

SPEAR-09-H042
3.3
Ballout top view
Figure 1. Ballout top view
Pin description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G
A
P _IO[ 21P _IO[ 33 P _IO[ 22 P _IO[ 23 P _IO[ 35 P _IO[ 42 P _IO[ 50 P _IO[ 52 P _IO[ 60 P _IO[ 67 P _IO[ 75 P _IO[ 77 P _IO[ 87 TEST0
SM IN C SM IN C SM IN C
S[3]
S[2]
S[ 1]
A
]
]
]
]
]
]
]
]
]
]
]
]
]
B
eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G _{SM ID A SM IN C SM IC L SM ID A}
P
_IO[ 17
]
P
_IO[ 30
]
P
_IO[ 32
]
P
_IO[ 19
]
P
_IO[ 28
]
P
_ IO [
]
41P
_IO[ 47
]
P
_IO[ 51P
]
_IO[ 59
]
P
_IO[ 66
]
P
_IO[ 73
]
P
_IO[ 79
]
P
_IO[ 89
]
TA
OUT
S[0]
K
TA IN
B
C
eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G _{TX_C L}
P _IO[ 14 P _IO[ 24 P _IO[ 26 P _IO[ 34 P _IO[ 27 P _IO[ 37 P _IO[ 39 P _IO[ 62 P _IO[ 58 P _IO[ 65 P _IO[ 72 P _IO[ 81 P _IO[ 91P _IO[ 97
]
]
]
]
]
]
]
]
]
]
]
]
]
]
K
TXD [0] TXD [1]
C
D
eA SIC G _{eA SIC G eA SIC G} eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G
P _IO[ 10
]
P _IO[ 7]
P _IO[ 9]
P _IO[ 13 P _IO[ 40 P _IO[ 54 P _IO[ 56 P _IO[ 46 P _IO[ 53 P _IO[ 64
]
]
]
]
]
]
]
P _IO[ 71P _IO[ 83 P _IO[ 93 P _IO[ 99
]
]
]
]
TXD [2]
TXD [3]
TX_EN
D
E
OVER C
OVER C
eA
SIC
G
e
A
SIC
G
eA SIC G
P _IO[ 15
eA SIC G
P _IO[ 18
eA
P_
SIC G
IO[ 48
eA
P_
SIC G
IO[ 44
eA
P_
SIC G
IO[ 45
eA
P_
SIC G
IO[ 63
eA SIC G
P _IO[ 70
eA
P_
SIC G
IO[ 85
eA
P_
SIC G
IO[ 95
eA SIC _
EXT_C
CRS
UR H 1 UR H 2 P _IO[ 8] P _IO[ 5]
]
]
]
]
]
]
]
]
]
LOC K
C OL ^{R X_C L} E
K
F
H OST1_ H OST2
eA
SIC
G
eA SIC G
P _IO[ 25
e
A
SIC
G
eA SIC G
P _IO[ 16
eA
P_
SIC G
IO[ 20
eA
P_
SIC G
IO[ 49
eA
P_
SIC G
IO[ 55
eA
P_
SIC G
IO[ 57
eA SIC G
P _IO[ 69
TD O
TD I
TM S R XD [0] R XD [1] R XD [2] F
VB US _VB US P _IO[ 4]
]
P _IO[ 6]
]
]
]
]
]
]
G
P LL_B
VB US
M
R
ESE
eA
SIC
G
eA SIC G
P _IO[ 31
eA
SIC
G
eA SIC G
P _IO[ 12
eA SIC G
P _IO[ 43
eA SIC G
P _IO[ 38
eA SIC G eA SIC G
P _IO[ 61P _IO[ 68
R TC K
YP A SS
T
P _IO[ 0]
]
P _IO[ 11 _]
]
]
]
]
TC K
nTR ST R XD [3] R X_D V R X_ER G
eA SIC G eA SIC G
H
v s s l_ 3 v
3 _ h0
v dd3 _ 3
v 3 _ h0
v ddl_ 1v
2 _ h0
v s s b_ 1v
2 _ h0
eA SIC G
P _IO[ 3]
eA SIC G
P _IO[ 2]
eA SIC G
P _IO[ 1]
P
_
IO
[
2
9
P
_
IO
[
3
6
v dd
vdd3v3 TEST3 TEST2 TEST1 M D C M D IO
SD A
H
]
]
J
H OST2
_D P
H OST2
_D M
vssc_1v vddb_1v vddc_1v
2_h0 2_h0 2_h0
R R EF
v dd
vdd3v3 vdd3v3 gnd
gnd
v dd
vdd3v3 vdd3v3
SC L
UA R T1_UA R T1_ _J
TXD R XD
eA SIC _
K
vssl_3v vdd3_3 vddl_1v vssb_1v vssc_1v
3_h1 v3_h1 2_h1 2_h1 2_h1
gnd
gnd
gnd
gnd
gnd
gnd
gnd
gnd
v dd3 v 3
P I_C LO
GP _IO[
5]
GP _IO[
4]
K
CK
L ^{H OST1_ H OST1_ vddb_1v vddc_1v gnd_us}
DP
DM
2_h1 2_h1
b
gnd
gnd
gnd
gnd
gnd
gnd
gnd
gnd
v dd
GP _IO[ GP _IO[ GP _IO[ 1 _L
3]
2]
]
M
gnde_u vdde3v ^{anavdd anagnd} vdd_us
sb
3 _ us b
_3v3_pll _3v3_pll
1600 1600
b
gnd
gnd
gnd
gnd
gnd
gnd
gnd
gnd
v dd3 v 3
GP _IO[ ^{M P M C M P M C}
0]
D A TA [1 D A TA [1
4]
5]
M
N
M C LK_i M C LK_ ^{digvdd_ diggnd_}
n
o ut
1v2_pll1 1v2_pll1
600
600
v dd
vdd2v5 vdd2v5
gnd
gnd
gnd
gnd
gnd
MPMC MPMC MPMC
gnd vdd3v3 D A TA [1 D A TA [1 D A TA [1 N
1]
2]
3]
P ^{vddc_1v vddb_1v vssc_1v vssb_1v vddl_1v vdd_dit vss_dit} vdd2v5 vdd
2_d
2_d
2_d
2_d
2_d
h
h
vdd2v5 vdd2v5 vdd2v5 vdd
v dd3 v 3
SSTL_ V
M PM C
D A TA [
M PM C
D A TA [1
P
R EF
9]
0]
R
D P LS
DM NS
v dd3 _ 3
v s s l_ 3 v
nM P M
C D YC S
M PM C
ADDR
M PM C
ADDR
M PM C
ADDR
M PM C
ADDR
M PM C
ADDR
MPMC MPMC MPMC
A D D R D A TA [1 D A TA [
M PM C
D A TA [
M PM C
D A TA [
M PM C
M PM C
R
v3_d
3_d _{OUT[3] OUT[0] OUT[3] OUT[6] OUT[9] OUT[12] OUT[14] ]}
3]
5]
7]
D QS[0] D QS[1]
T
v dd1v 2
da t e _ o
ci
_
s
gnde _ d
ate_o sc
i
gnd_
e_o
da
sc
t
i
nM P M nM P M nM P M M P M C
C D YC S C D YC S C C A SO A D D R
OUT[1] OUT[2] UT OUT[2]
M PM C
ADDR
OUT[5]
M PM C
ADDR
OUT[8]
MPMC MPMC MPMC
A D D R A D D R D A TA [
OUT[11 OUT[13] 0]
M PM C
D A TA [
2]
M PM C
D A TA [
4]
M PM C
D A TA [
6]
M PM C
DQM O
UT[0]
M PM C
D A TA [
8]
T
nM P M nM P M nM P M M P M C M P M C M P M C M P M C M P M C M P M C nM P M M P M C nM P M M P M C M P M C
U
R TC XI
R TC XO
v dd_ da t
e_o sci
C D YC S C WEOU C R A SO
ADDR
ADDR
ADDR
A D D R C KEOU C KEOU C C LKO C LKOU C C LKO C LKOU D QM O
U
OUT[0] T
UT OUT[1] OUT[4] OUT[7] OUT[10] T[0]
T[1] UT[1] T[1] UT[0] T[0] UT[1]
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