SPEAR-09-H042 Datasheet, PDF (1/16 Pages) STMicroelectronics – SPEAr™ Head200, ARM 926, 200 K customizable eASIC™ gates, large IP portfolio SoC

SPEAR-09-H042
SPEAr™ Head200
ARM 926, 200 K customizable eASIC™ gates, large IP portfolio SoC
Data Brief
Features
■ ARM926EJ-S - f_MAX 266 MHz,
32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and
JTAG interfaces
■ 200K customizable equivalent ASIC gates
(16K LUT equivalent) with 8 channels internal
DMA high speed accelerator function and 87
dedicated general purpose I/Os
■ Multilayer AMBA 2.0 compliant bus with
f_MAX 133 MHz
■ Programmable internal clock generator with
enhanced PLL function, specially optimized for
E.M.I. reduction
■ 16 KB single port SRAM embedded
■ Dynamic RAM interface:
8/16 bit DDR, 8/16 bit SDRAM
■ SPI interface connecting serial ROM and Flash
devices
■ 2 USB 2.0 Host independent ports with
integrated PHYs
■ USB 2.0 device with integrated PHY
■ Ethernet MAC 10/100 with MII management
interface
■ 1 independent UART up to 115 Kbps (software
flow control mode)
■ I²C master mode, fast and slow speed
■ 6 general purpose I/Os
LFBGA289
■ Real time clock
■ WatchDog
■ 4 general purpose timers
■ Operating temperature: - 40 to 85 °C
■ Package: LFBGA289 (15x15x1.7mm pitch
0.8mm)
Description
SPEAr Head200 is a powerful digital engine
belonging to SPEAr family, the innovative
customizable system-on-chip.
The device integrates an ARM core with a large
set of proven IPs (Intellectual Properties) and a
configurable logic block that allows very fast
customization of unique and/or proprietary
solutions, with low effort and low investment.
Optimized for embedded applications.
Table 1. Device summary
Order code
SPEAR-09-H042
Package
LFBGA289 (15x15x1.7mm)
Packing
Tray
January 2008
Rev 1
For further information contact your local STMicroelectronics sales office.
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