MIC2593 Datasheet, PDF (13/26 Pages) STMicroelectronics – Dual-Slot PCI Hot Plug Controller

MIC2593
Slot B, CFILTER[B] is located at Pin 35. For a given response
time, the value for CFILTER[A/B] is given by:
CFILTER[A / B](µF) = ^{tFLT[A /B](ms) × IFILTER (µA)}
V_FILTER (V) × 10³
where t_FLT[A/B] is the selected overcurrent response time
and I_FILTER and V_FILTER are specified in the “Electrical
Characteristics” table.
Thermal Shutdown
The internal +12V, –12V, and V_AUX MOSFETs are protected
against damage not only by current limiting, but by dual-mode
overtemperature protection as well. Each slot controller on
the MIC2593 is thermally isolated from the other. Should an
overcurrent condition raise the junction temperature of one
slot’s controller and internal pass elements to 140°C, all of the
outputs for that slot (including V_AUX) will be shut off, and the
slot’s /FAULT output will be asserted. The other slot’s opera-
tion will remain unaffected. However, should the MIC2593’s
overall die temperature exceed 160°C, both slots (all outputs,
including V_AUXA and V_AUXB) will be shut off, whether or not a
current limit condition exists. A 160°C overtemperature con-
dition additionally sets the overtemperature bit (OT_INT) in
the Common Status Register.
Output Power-Good Status
For the MIC2593, “Power-is-Good” is valid on a slot when the
outputs of the four MAIN supplies (12V, –12V, 5V, and 3.3V)
and the auxiliary supply output are all above their respective
power-good thresholds specified in the “Electrical Character-
istics” table. The power-good status of either slot is verified by
polling the CNTRL[A/B] Register Bits D[7:6]. CNTRL[A/B]
Register Bits D[7] and D[6] indicate output power-good status
for the AUX supply and MAIN supplies, respectively. Figure
7 below illustrates an equivalent logic circuit that determines
the output power-good status for the MAIN and AUX supplies.
General Purpose Input (GPI) Pins
Two pins on the MIC2593 are available for use as GPI pins.
The logic state of each of these pins can be determined by
polling Bits [4:5] of Common Status Register. Both of these
Micrel
inputs are compliant to 3.3V. If unused, connect the GPI[A/B]
pins to GND.
Fault Reporting and /INT Interrupt Generation
SMI-only Control Applications
In applications where the MIC2593 is controlled only by the
SMI, the ON[A/B] and AUXEN[A/B] should be connected to
GND as shown in Figure 6. In this case, the MIC2593’s
/FAULT[A/B] outputs and STAT[A/B] Register Bit D[7]
(FAULT[A/B]) are not activated, as fault status is determined
by polling STAT[A/B] Register Bits D[4:0] and CS (Common
Status) Register Bits D[2:1]. Individual fault bits in STAT[A/B]
and CS are asserted after power-on-reset when:
Either or both CNTRL[A/B] Register Bits D[1:0] are asserted,
AND
• 12VIN[A/B], 12MVIN[A/B], 5VIN[A/B], 3VIN[A/B],
or VSTBY[A/B] input voltage is lower than its
respective ULVO threshold, OR
• The fast OC circuit breaker[A/B] has tripped, OR
• The slow OC circuit breaker[A/B] has tripped AND
its filter timeout has expired, OR
• The slow OC circuit breaker[A/B] has tripped AND
Slot[A/B] die temperature exceeds 140°C, OR
• The MIC2593’s global die temperature exceeds
160°C
To clear any one or all STAT[A/B] Register Bits D[4:0] and/or
CS Register Bits D[2:1] once asserted, a software subroutine
can perform an “echo reset” where a Logical “1” is written
back to those register bit locations that have indicated a fault.
The open-drain, active-LOW /INT output signal is activated
after power-on-reset when the INTMSK bit (CS Register Bit
D[3]) has been reset to Logical “0”. Once activated, the /INT
output is asserted by any one of the fault conditions listed
above and de-asserted when one or all STAT[A/B] Register
Bits D[4:0] and/or CS Register Bits D[2:1] are reset upon the
execution of an SMBus “echo reset” WRITE_BYTE cycle.
V_STBY[A/B]
3VAUX_UV[A/B]⁽¹⁾
AUX[A/B]PG⁽²⁾
April 2004
12VOUT_UV[A/B]⁽¹⁾
3VOUT_UV[A/B]⁽¹⁾
V_STBY[A/B]
MAIN[A/B]PG⁽³⁾
Notes:
1. Internal flag
2. CNTRL[A/B] Register Bit D[7]
3. CNTRL[A/B] Register Bit D[6]
Figure 7. Power-Good Status Logic Diagram
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