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ST7263BHX_09 Datasheet, PDF (126/186 Pages) STMicroelectronics – Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI and I²C
On-chip peripherals
Figure 50. ADC block diagram
fCPU
DIV 4
fADC
ST7263Bxx
COCO 0 ADON 0 CH3 CH2 CH1 CH0 ADCCSR
4
AIN0
HOLD CONTROL
AIN1
RADC
ANALOG
MUX
ANALOG TO DIGITAL
CONVERTER
AINx
CADC
ADCDR D7 D6 D5 D4 D3 D2 D1 D0
Digital A/D conversion result
The conversion is monotonic, meaning that the result never decreases if the analog input
does not and never increases if the analog input does not.
If the input voltage (VAIN) is greater than or equal to VDDA (high-level voltage reference) then
the conversion result in the DR register is FFh (full scale) without overflow indication.
If input voltage (VAIN) is lower than or equal to VSSA (low-level voltage reference) then the
conversion result in the DR register is 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDR
register. The accuracy of the conversion is described in the parametric section.
RAIN is the maximum recommended impedance for an analog input signal. If the impedance
is too high, this will result in a loss of accuracy due to leakage and sampling not being
completed in the allotted time.
A/D conversion phases
The A/D conversion is based on two conversion phases as shown in Figure 51:
● Sample capacitor loading [duration: tLOAD]
During this phase, the VAIN input voltage to be measured is loaded into the CADC
sample capacitor.
● A/D conversion [duration: tCONV]
During this phase, the A/D conversion is computed (8 successive approximations
cycles) and the CADC sample capacitor is disconnected from the analog input pin to get
the optimum analog to digital conversion accuracy.
While the ADC is on, these two phases are continuously repeated.
At the end of each conversion, the sample capacitor is kept loaded with the previous
measurement load. The advantage of this behavior is that it minimizes the current
consumption on the analog pin in case of single input channel measurement.
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Doc ID 7516 Rev 8