ST7263BHX_09 Datasheet, PDF (121/186 Pages) STMicroelectronics – Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI and I²C

ST7263Bxx
On-chip peripherals
I²C Status register 2 (SR2)
Reset value: 0000 0000 (00h)
7
0
0
0
AF
STOPF
Read only
ARLO
BERR
0
GCAL
[7:5] Reserved. Forced to 0 by hardware.
4 AF Acknowledge failure.
This bit is set by hardware when no acknowledge is returned. An interrupt is
generated if ITE=1. It is cleared by software reading SR2 register or by hardware
when the interface is disabled (PE=0).
0: No acknowledge failure
1: Acknowledge failure
Note: While AF=1, the SCL line may be held low due to SB or BTF flags that are
set at the same time. It is then necessary to release both lines by software.
3 STOPF Stop detection (Slave mode).
This bit is set by hardware when a Stop condition is detected on the bus after an
acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by
software reading SR2 register or by hardware when the interface is disabled
(PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
Doc ID 7516 Rev 8
121/186