UM0238 Datasheet, PDF (12/20 Pages) STMicroelectronics – STR91x demonstration software

Running the demonstrations
STR91x demonstration software
2.2
Clock sources
2.2.1
Clock control
The STR91x internal clocks are derived from an on-board 25 MHz crystal source.
In this demo application, the system clock is configured as follow:
● HCLK frequency is set to 96 MHz
● FMICLK frequency is set to 96 MHz
● PCLK is set to 48 MHz
● USB clock (CK_USB) is set to 48 MHz (internal clock)
Only the RTC is clocked by a 32 kHz external oscillator.
Figure 4. Clock control
X1_CPU
X2_CPU
MAIN ^{4 to 25 MHz}
OSC _fOSC
MII_PHYCLK
25 MHz
PHYSEL
MCLKSEL
f_OSC
PLL
f_PLL
f_RTC
RCLKDIV RCLK
(1,2,4,8,16,1024)
f_MSTR
X1_RTC
X2_RTC
RTC 32.768
OSC ^kHz
to RTC
to WDG (software
selectable in WDG
register)
AHBDIV
(1,2,4)
HCLK
Peripheral
Clock
Gating
HCLK
to AHB
peripherals
APBDIV
(1,2,4,8)
PCLK
Peripheral
Clock
Gating
PCLK
to APB
peripherals
FMICLK
Peripheral
Clock
FMICLK
1/2
Gating to Flash Memory
Interface
Special interrupt
mode control
CPUCLK
to CPU
EXTCLK_T0T1
EXTCLK_T2T3
1/2
16-bit prescaler
16-bit prescaler
BRCLK
Baud rate clock to UARTs
Peripheral
Clock
TIM01CLK
Gating to TIM0 & TIM1
Peripheral
Clock
TIM23CLK
Gating to TIM2 & TIM3
USB_CLK48M
1/2
Peripheral
Clock
48 MHz USBCLK
Gating ^{to USB block}
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