CRX14_05 Datasheet, PDF (12/40 Pages) STMicroelectronics – Low Cost ISO14443 type-B Contactless Coupler Chip with Anti-Collision, CRC Management and Anti-Clone Function

CRX14
CRX14 I²C PROTOCOL DESCRIPTION
The CRX14 is compatible with the I²C serial bus
memory standard, which is a two-wire serial inter-
face that uses a bi-directional data bus and serial
clock.
The CRX14 has a pre-programmed, 4-bit identifi-
cation code, ’1010’ (as shown in Table 6.), that
corresponds to the I²C bus definition. With this
code and the three Chip Enable inputs (E2, E1,
E0) up to eight CRX14 devices can be connected
to the I²C bus, and selected individually.
The CRX14 behaves as a slave device in the I²C
protocol, with all CRX14 operations synchronized
to the serial clock.
I²C Read and Write operations are initiated by a
START condition, generated by the bus master.
The START condition is followed by the Device
Select Code and by a Read/Write bit (R/W). It is
terminated by an acknowledge bit. The Device Se-
lect Code consists of seven bits (as shown in Ta-
ble 6.):
■ the Device Code (first four bits)
■ plus three bits corresponding to the states of
the three Chip Enable inputs, E2, E1 and E0,
respectively
When data is written to the CRX14, the device in-
serts an acknowledge bit (9th bit) after the bus
master’s 8-bit transmission.
When the bus master reads data, it also acknowl-
edges the receipt of the data Byte by inserting an
acknowledge bit (9th bit).
Data transfers are terminated by a STOP condition
after an ACK for Write, or after a NoACK for Read.
The CRX14 supports the I²C protocol, as summa-
rized in Figure 7.
Any device that sends data on to the bus, is de-
fined as a transmitter, and any device that reads
the data, as a receiver.
The device that controls the data transfer is known
as the master, and the other, as the slave. A data
transfer can only be initiated by the master, which
also provides the serial clock for synchronization.
The CRX14 is always a slave device in all I²C com-
munications. All data are transmitted Most Signifi-
cant Bit (MSB) first.
Table 6. Device Select Code
Device Code
Chip Enable
RW
b7
b6
b5
b4
b3
b2
b1
b0
CRX14 Select
1
0
1
0
E2
E1
E0
RW
I²C Start Condition
START is identified by a High-to-Low transition of
the Serial Data line, SDA, while the Serial Clock,
SCL, is stable in the High state. A START condi-
tion must precede any data transfer command.
The CRX14 continuously monitors the SDA and
SCL lines for a START condition (except during
Radio Frequency data exchanges), and will not re-
spond unless one is sent.
I²C Stop Condition
STOP is identified by a Low-to-High transition of
the Serial Data line, SDA, while the Serial Clock,
SCL, is stable in the High state.
A STOP condition terminates communications be-
tween the CRX14 and the bus master.
A STOP condition at the end of an I²C Read com-
mand, after (and only after) a NoACK, forces the
CRX14 into its stand-by state.
A STOP condition at the end of an I²C Write com-
mand triggers the Radio Frequency data ex-
change between the CRX14 and the PICC.
I²C Acknowledge Bit (ACK)
An acknowledge bit is used to indicate a success-
ful data transfer on the I²C bus.
The bus transmitter, either master or slave, releas-
es the Serial Data line, SDA, after sending 8 bits of
data. During the 9th clock pulse the receiver pulls
the SDA line Low to acknowledge the receipt of
the 8 data bits.
I²C Data Input
During data input, the CRX14 samples the SDA
bus signal on the rising edge of the Serial Clock,
SCL. For correct device operation, the SDA signal
must be stable during the Low-to-High Serial
Clock transition, and the data must change only
when the SCL line is Low
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