CRX14_05 Datasheet, PDF (10/40 Pages) STMicroelectronics – Low Cost ISO14443 type-B Contactless Coupler Chip with Anti-Collision, CRC Management and Anti-Clone Function

CRX14
Input/Output Frame Register (01h)
The Input/Output Frame Register is a 36-Byte
buffer that is accessed serially from Byte 0 through
to Byte 35 (see Table 4.). It is located at the I²C ad-
dress 01h.
The Input/Output Frame Register is the buffer in
which the CRX14 stores the data Bytes of the re-
quest frame to be sent to the PICC. It automatical-
ly stores the data Bytes of the answer frame
received from the PICC. The first Byte (Byte 0) of
the Input/Output Frame Register is used to store
the frame length for both transmission and recep-
tion.
When accessed in I²C Write mode , the register
stores the request frame Bytes that are to be
transmitted to the PICC. Byte 0 must be set with
the request frame length (in Bytes) and the frame
is stored from Byte 1 onwards. At the end of the
transmission, the 16-bit CRC is automatically add-
ed. After the transmission, the CRX14 wait for the
PICC to send back an answer frame. When cor-
rectly decoded, the PICC answer frame Bytes are
stored in the Input/Output Frame Register from
Byte 1 onwards. Byte 0 stores the number of Bytes
received from the PICC.
When accessed in I²C Read mode, the Input/Out-
put Register sends back the last PICC answer
frame Bytes, if any, with Byte 0 transmitted first.
The 16-bit CRC is not stored, and it is not sent
back on the I²C bus.
The Input/Output Frame Register is set to all 00h
between transmission and reception. If there is no
answer from the PICC, Byte 0 is set to 00h. In the
case of a CRC error, Byte 0 is set to FFh, and the
data Bytes are discarded and not appended in the
register.
The CRX14 Input/Output Frame Register is so de-
signed as to generate all the ST short range mem-
ory command frames. It can also generate all
standardized ISO14443 type-B command frames
like REQB, SLOT-MARKER, ATTRIB, HALT, and
get all the answers like ATQB, or answer to AT-
TRIB. All ISO14443 type-B compliant PICCs can
be accessed by the CRX14 provided that their
data frame exchange is not longer than 35 Bytes
in both request and answer.
Table 4. Input/Output Frame Register Description
Byte 0
Byte 1
Byte 2
Byte 3
...
Byte 34
Byte 35
Frame Length
First data Byte
Second data Byte
Last data Byte
<------------- Request and Answer Frame Bytes exchanged on the RF ------------->
00h No Byte transmitted
FFh CRC Error
xxh Number of transmitted Bytes
Authenticate Register (02h)
The Authenticate Register is used to trigger the
complete authentication exchange between the
CRX14 and the secured ST short range memory.
It is located at the I²C address 02h.
The Authentication system is based on a propri-
etary challenge/response mechanism that allows
the application software to authenticate a secured
ST short range memory of the SRXxxx family. A
reader designed with the CRX14 can check the
authenticity of a memory device and protect the
application system against silicon copies or emu-
lators.
A complete description of the Authentication sys-
tem is available under Non Disclosure Agreement
(NDA) with STMicroelectronics. For more details
about this CRX14 function, please contact the
nearest STMicroelectronics sales office.
Slot Marker Register (03h)
The slot Marker Register is located at the I²C ad-
dress 03h. It is used to trigger an automated anti-
collision sequence between the CRX14 and any
ST short range memory present in the electromag-
netic field. With one I²C access, the CRX14
launches a complete stream of commands starting
from
PCALL16(),
SLOT_MARKER(1),
SLOT_MARKER(2) up to SLOT_MARKER(15),
and stores all the identified Chip_IDs into the In-
put/Output Frame Register (I²C address 01h).
This automated anti-collision sequence simplifies
the host software development and reduces the
time needed to interrogate the 16 slots of the ST-
Microelectronics anti-collision mechanism.
When accessed in I²C Write mode, the Slot Marker
Register starts generating the sequence of anti-
collision commands. After each command, the
CRX14 wait for the ST short range memory an-
swer frame which contains the Chip_ID. The valid-
ity of the answer is checked and stored into the
corresponding Status Slot Bit (Byte 1 and Byte 2
as described in Table 6.). If the answer is correct,
the Status Slot Bit is set to ‘1’ and the Chip_ID is
stored into the corresponding Slot_Register. If no
answer is detected, the Status Slot Bit is set to ‘0’,
and the corresponding Slot_Register is set to 00h.
10/40