PSD813F2 Datasheet, PDF (11/110 Pages) STMicroelectronics – Flash In-System Programmable ISP Peripherals For 8-bit MCUs

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Pin Name Pin Type
Description
Reset
48
I
Resets I/O Ports, PLD macrocells and some of the Configuration Registers. Must be Low
at Power-up.
These pins make up Port A. These port pins are configurable and can have the following
functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellAB0-7) outputs.
PA0
29
Inputs to the PLDs.
PA1
28
PA2
27
Latched address outputs (see Table 6).
PA3
PA4
PA5
25
24
23
I/O Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA in
burst mode.
PA6
22
PA7
21
As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.
D0/A16-D3/A19 in M37702M2 mode.
Peripheral I/O mode.
Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However,
PA4-PA7 can be configured as CMOS or Open Drain Outputs.
These pins make up Port B. These port pins are configurable and can have the following
functions:
PB0
7
MCU I/O – write to or read from a standard output or input port.
PB1
6
PB2
5
CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.
PB3
PB4
4
3
I/O _{Inputs to the PLDs.}
PB5
2
PB6
52
Latched address outputs (see Table 6).
PB7
51
Note: PB0-PB3 can only output CMOS signals with an option for high slew rate.
However, PB4-PB7 can be configured as CMOS or Open Drain Outputs.
PC0 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC0) output.
PC0
20 I/O _{Input to the PLDs.}
TMS Input² for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
PC1 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC1) output.
PC1
19 I/O _{Input to the PLDs.}
TCK Input² for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
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