PSD813F2 Datasheet, PDF (1/110 Pages) STMicroelectronics – Flash In-System Programmable ISP Peripherals For 8-bit MCUs

PSD813F2, PSD833F2
PSD834F2, PSD853F2, PSD854F2
Flash In-System Programmable (ISP)
Peripherals for 8-bit MCUs, 5V
PRELIMINARY DATA
FEATURES SUMMARY
■ FLASH IN-SYSTEM PROGRAMMABLE (ISP)
PERIPHERAL FOR 8-BIT MCUS
■ DUAL BANK FLASH MEMORIES
– UP TO 2 Mbit OF PRIMARY FLASH
MEMORY (8 Uniform Sectors, 32K x8)
– UP TO 256 Kbit SECONDARY FLASH
MEMORY (4 Uniform Sectors)
– Concurrent operation: READ from one
memory while erasing and writing the
other
■ UP TO 256 Kbit BATTERY-BACKED SRAM
■ 27 RECONFIGURABLE I/O PORTS
■ ENHANCED JTAG SERIAL PORT
■ PLD WITH MACROCELLS
– Over 3000 Gates of PLD: CPLD and
DPLD
– CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs)
– DPLD - user defined internal chip select
decoding
■ 27 INDIVIDUALLY CONFIGURABLE I/O
PORT PINS
The can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os.
– 16 of the I/O ports may be configured as
open-drain outputs.
■ IN-SYSTEM PROGRAMMING (ISP) WITH
JTAG
– Built-in JTAG compliant serial port allows
full-chip In-System Programmability
– Efficient manufacturing allow easy
product testing and programming
– Use low cost FlashLINK cable with PC
■ PAGE REGISTER
– Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
■ PROGRAMMABLE POWER MANAGEMENT
Figure 1. Packages
PQFP52 (M)
PLCC52 (J)
TQFP64 (U)
■ HIGH ENDURANCE:
– 100,000 Erase/WRITE Cycles of Flash
Memory
– 1,000 Erase/WRITE Cycles of PLD
– 15 Year Data Retention
■ 5V±10% SINGLE SUPPLY VOLTAGE
■ STANDBY CURRENT AS LOW AS 50µA
June 2004
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.