M29F040 Datasheet, PDF (11/31 Pages) STMicroelectronics – 4 Mbit 512Kb x8, Uniform Block Single Supply Flash Memory

M29F040
Table 12A. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)⁽³⁾
M29F040
Symbol Alt
Parameter
Test Condition
-70
-90
V_CC = 5V ± 5% V_CC = 5V ± 10% ^Unit
Standard
Interface
Standard
Interface
Min Max Min Max
tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL 70
90
ns
t_AVQV t_ACC Address Valid to Output Valid
E = V_IL, G = V_IL
70
90 ns
t_ELQX ⁽¹⁾ t_LZ Chip Enable Low to Output Transition
G = V_IL
0
0
ns
t_ELQV ⁽²⁾ t_CE Chip Enable Low to Output Valid
G = V_IL
70
90 ns
t_GLQX ⁽¹⁾
t_OLZ
Output Enable Low to Output
Transition
E = V_IL
0
0
ns
t_GLQV ⁽²⁾ t_OE Output Enable Low to Output Valid
E = V_IL
30
35 ns
t_EHQX
t_OH
Chip Enable High to Output
Transition
G = V_IL
0
0
ns
t_EHQZ ⁽¹⁾ t_HZ Chip Enable High to Output Hi-Z
G = V_IL
20
20 ns
t_GHQX
t_OH
Output Enable High to Output
Transition
E = V_IL
0
0
ns
t_GHQZ ⁽¹⁾ t_DF Output Enable High to Output Hi-Z
E = V_IL
20
20 ns
t_AXQX
t_OH
Address Transition to Output
Transition
E = V_IL, G = V_IL 20
20
ns
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
3. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%.
Block Erase (BE) instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 5555h
on third cycle after the two coded cycles. The Block
Erase Confirm command 30h is written on sixth
cycle after another two coded cycles. During the
input of the second command an address within
the block to be erased is given and latched into the
memory. Additional Block Erase confirm com-
mands and block addresses can be written sub-
sequently to erase other blocks in parallel, without
further coded cycles. The erase will start after an
Erase timeout period of about 100µs. Thus, addi-
tional Block Erase commands must be given within
this delay. The input of a new Block Erase com-
mand will restart the timeout period. The status of
the internal timer can be monitored through the
level of DQ3, if DQ3 is ’0’ the Block Erase Com-
mand has been given and the timeout is running, if
DQ3 is ’1’, the timeout has expired and the P/E.C
is erasing the block(s). Before and during Erase
timeout, any command different from 30h will abort
the instruction and reset the device to read array
mode. It is not necessary to program the block with
00h as the P/E.C. will do this automatically before
erasing to FFh. Read operations after the sixth
rising edge of W or E output the status register bits.
During the execution of the erase by the P/E.C., the
memory accepts only the ES (Erase Suspend) and
RST (Reset) instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The Toggle Bit DQ6 toggles
during the erase operation. It stops when erase is
completed. After completion the Status Register
bit DQ5 returns ’1’ if there has been an Erase
Failure because erasure has not completed even
after the maximum number of erase cycles have
been executed. In this case, it will be necessary to
input a Reset (RST) to the command interface in
order to reset the P/E.C.
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